Processor IA Core C-State Rules

The following are general rules for all processor IA core C-states, unless specified otherwise:

• A processor IA core transitions to C0 state when:
  • An interrupt occurs
  • There is an access to the monitored address if the state was entered using an MWAIT/Timed MWAIT instruction.
  • The deadline corresponding to the Timed MWAIT instruction expires.
• Any interrupt coming into the processor package may wake any processor IA core.
• A system reset re-initializes all processor IA cores.

Core C-State Auto-Demotion

In general, deeper C-states, such as C6, have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or inefficient usage of deeper C-states have a negative impact on battery life and idle power. To increase residency and improve battery life and idle power in deeper C-states, the processor supports C-state auto-demotion.

C-State auto-demotion:

• C6 to C1/C1E

The decision to demote a processor IA core from C6 to C1/C1E is based on each processor IA core’s immediate residency history. Upon each processor IA core C6 request, the processor IA core C-state is demoted to C1 until a sufficient amount of residency has been established. At that point, a processor IA core is allowed to go into C6. If the interrupt rate experienced on a processor IA core is high and the processor IA core is rarely in a deep C-state between such interrupts, the processor IA core can be demoted to a C1 state.

This feature is disabled by default. Refer the Firmware Architecture Specifications for more details on how to enable this.

There are also Module C-states related to the core C states.