Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
Datasheet
Channels and Supported Transactions
An eSPI channel provides a means to allow multiple independent flows of traffic to share the same physical bus. Refer to the eSPI specification for more detail.
Each of the channels has its dedicated resources such as queue and flow control. There is no ordering requirement between traffic from different channels.
The number of types of channels supported by a particular eSPI slave is discovered through the GET_CONFIGURATION command issued by the PCH to the eSPI slave during initialization.
Below a table summarizes the eSPI channels and supported transactions.
CH # | Channel | Posted Cycles Supported | Non-Posted Cycles Supported |
---|---|---|---|
0 | Peripheral | Memory Write, Completions | Memory Read, I/O Read/Write |
1 | Virtual Wire | Virtual Wire GET/PUT | N/A |
2 | Out-of-Band Message | SMBus Packet GET/PUT | N/A |
3 | Flash Access | N/A | Flash Read, Write, Erase |
N/A | General | Register Accesses | N/A |
Peripheral Channel (Channel 0) Overview
The Peripheral channel performs the following functions:
- Target for PCI Device D31:F0: The eSPI controller duplicates the legacy PCI Configuration space registers. These registers are mostly accessed via the BIOS, though some are accessed via the OS as well.
- Tunnel all Host to eSPI Slave (EC/SIO) Debug Device Accesses: These include various programmable and fixed I/O ranges as well as programmable Memory ranges. The programmable ranges and their enables reside in the PCI Configuration space.
- Tunnel all Accesses from the eSPI Slave to the Host. These include Memory Reads and Writes.
Virtual Wire Channel (Channel 1) Overview
The Virtual Wire channel uses a standard message format to communicate several types of signals between the components on the platform.
- Sideband and GPIO Pins: System events and other dedicated signals between the PCH and eSPI slave. These signals are tunneled between the 2 components over eSPI.
- Serial IRQ Interrupts: Interrupts are tunneled from the eSPI slave to the PCH. Both edge and triggered interrupts are supported.
eSPI Virtual Wires (VW)
Below table summarizes the PCH virtual wires in eSPI mode.
Virtual Wire | PCH Pin Direction | Reset Control | Pin Retained in PCH (For Use by Other Components) |
---|---|---|---|
SUS_STAT# | Output | ESPI_RST0_N | No |
SUSPWRDNACK | Output | ESPI_RST0_N | No |
PLTRST# | Output | ESPI_RST0_N | Yes |
PME# (eSPI Peripheral PME) | Input | ESPI_RST0_N | N/A |
WAKE# | Input | ESPI_RST0_N | No |
SMI# | Input | PMC_PLTRST_N | N/A |
SCI# | Input | PMC_PLTRST_N | N/A |
RCIN# | Input | PMC_PLTRST_N | No |
SLAVE_BOOT_LOAD_DONE | Input | ESPI_RST0_N | N/A |
SLAVE_BOOT_LOAD_STATUS | Input | ESPI_RST0_N | N/A |
HOST_RST_WARN | Output | PMC_PLTRST_N | N/A |
HOST_RST_ACK | Input | PMC_PLTRST_N | N/A |
OOB_RST_WARN | Output | ESPI_RST0_N | N/A |
OOB_RST_ACK | Input | ESPI_RST0_N | N/A |
HOST_C10 | Output | PMC_PLTRST_N | N/A |
ERROR_NONFATAL | Input | ESPI_RST0_N | N/A |
ERROR_FATAL | Input | ESPI_RST0_N | N/A |
Interrupt Events
eSPI supports both level and edge-triggered interrupts. Refer to the eSPI Specification for details on the theory of operation for interrupts over eSPI.
The PCH eSPI controller will issue a message to the PCH interrupt controller when it receives an IRQ group in its VW packet, indicating a state change for that IRQ line number.
The eSPI slave can send multiple VW IRQ index groups in a single eSPI packet, up to the Operating Maximum VW Count programmed in its Virtual Wire Capabilities and Configuration Channel.
The eSPI controller acts only as a transport for all interrupt events generated from the slave. It does not maintain interrupt state, polarity or enable for any of the interrupt events.
Out-of-Band Channel (Channel 2) Overview
The Out-of-Band channel performs the following functions:
- Tunnel PCH Temperature Data to the eSPI Slave: The eSPI controller stores the PCH temperature data internally and sends it to the slave using a posted OOB message when a request is made to a specific destination address.
- Tunnel PCH RTC Time and Date Bytes to the eSPI Slave: the eSPI controller captures this data internally at periodic intervals from the PCH RTC controller and sends it to the slave device using a posted OOB message when a request is made to a specific destination address.
PCH Temperature Data Over eSPI OOB Channel
eSPI controller supports the transmitting of PCH thermal data to the eSPI slave. The thermal data consists of 1 byte of PCH temperature data that is transmitted periodically (~1 ms) from the thermal sensor unit.
The packet formats for the temperature request from the eSPI slave and the PCH response back are shown in following two figures.
PCH RTC Time/Date to EC Over eSPI OOB Channel
The PCH eSPI controller supports the transmitting of PCH RTC time/date to the eSPI slave. This allows the eSPI slave to synchronize with the PCH RTC system time. Moreover, using the OOB message channel allows reading of the internal time when the system is in Sx states.
The RTC time consists of 7 bytes: seconds, minutes, hours, day of week, day of month, month and year. The controller provides all the time/date bytes together in a single OOB message packet. This avoids the boundary condition of possible roll over on the RTC time bytes if each of the hours, minutes, and seconds bytes is read separately.
The packet formats for the RTC time/date request from the eSPI slave and the PCH response back to the device are shown in following two figures.
- DS: Daylight Savings. A 1 indicates that Daylight Saving has been comprehended in the RTC time bytes. A 0 indicates that the RTC time bytes do not comprehend the Daylight Savings.
- HF: Hour Format. A 1 indicates that the Hours byte is in the 24-hr format. A 0 indicates that the Hours byte is in the 12-hr format. In 12-hr format, the seventh bit represents AM when it is a 0 and PM when it is a 1.
- DM: Data Mode. A 1 indicates that the time byte are specified in binary. A 0 indicates that the time bytes are in the Binary Coded Decimal (BCD) format.