| Operating Voltage | Voltage Range for Processor Operating Mode | All | 0 | 1.8 | 2 | V | 1,2,3, 7,11 |
| IccMAX | Maximum Processor ICC | 4 Core(6 W) | — | — | 33 | A | 4,6,7,10 |
| 2 Core(6 W) | | | 22 | A | |
| 4 Core(10 W) | | | 35 | A | |
| 2 Core(10 W) | | | 25 | A | |
| IccTDP | Thermal Design Current for processor VccIN Rail | — | — | — | 10 | A | |
| TOBVCC | Voltage Tolerance | PS0,PS1 | — | — | ±20 | mV | 3, 6, 8 |
| PS2,PS3 | | | ±35 | | |
| Ripple | Ripple Tolerance | PS0,PS1 | | | ±15 | mV | 3, 6, 8 |
| PS2,PS3 | | | ±30 | | |
| DC_LL | Loadline slope within the VR regulation loop capability | — | 0 | — | 2 | mΩ | 9,12,13 |
| AC_LL | AC Loadline (<10 MHz) | — | — | — | 5 | mΩ | 9,12,13 |
| VOS | Max Overshoot Voltage | | | | 200 | mV | |
| T_OVS_TDP_MAX | Max Overshoot time TDP/virus mode | — | — | — | 500 | μs | |
| V_OVS TDP_MAX/virus_MAX | Max Overshoot at TDP/virus mode | — | — | — | 10 | % | |
- All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
- Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or low-power states).
- The voltage specification requirements are measured across Vcc_SENSE and Vss_SENSE as near as possible to the processor with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
- Processor VccIN VR to be designed to electrically support this current.
- Processor VccIN VR to be designed to thermally support this current indefinitely.
- Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated.
- Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
- PSx refers to the voltage regulator power state as set by the SVID protocol.
- LL measured at sense points.
- Typ column represents IccMAX for commercial application it is NOT a specification - it is a characterization of limited samples using limited set of benchmarks that can be exceeded.
- Operating voltage range in steady state.
- LL spec values should not be exceeded. If exceeded, power, performance and reliability penalty are expected.
- Load Line (AC/DC) should be measured by the VRTT tool and programmed accordingly via the BIOS Load Line override setup options. AC/DC Load Line BIOS programming directly affects operating voltages (AC) and power measurements (DC). A superior board design with a shallower AC Load Line can improve on power, performance and thermals.
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