Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

Intel® Trace Hub (Intel® TH)

JTAG, DBG_​PMODE and CFG Testability Signal 

Signal Name

Type1

Description

CPU_​JTAG_​TCK

IN

Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic

PCH_​JTAG_​X

IN

Pin used to support Merged Debug Port topology

CPU_​JTAG_​TMS

PCH_​JTAG_​TMS

IN

Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations

CPU_​JTAG_​TDI

PCH_​JTAG_​TDI

IN

Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI

CPU_​JTAG_​TDO

PCH_​JTAG_​TDO

OUT

Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard

CPU_​JTAG_​TRST_​N

PCH_​JTAG_​TRST_​N

IN

Test Reset (active low)

DBG_​PMODE2

IN/OUT

Debug Power Mode Indicator. Signal is used to transmit Compute Die and PCH power/reset information to the debug tool

CFG[00:15]3

IN/OUT

CFG (Parallel Trace Interface) signals are used for Compute Die Tracing

Notes:
  1. Directions are specified at Processor
  2. DBG_​PMODE (HOOK 6) part of Miscellaneous Signal
  3. CFG[00:15] part from Trace Signal