Tir

Input Time Rise

50

500

ps

Tif

Input Time Fall

50

500

ps

Tidr

Input Delay Rise

0.3

2.5

ns

Tidf

Input Delay Fall

0.3

2.5

ns

CLKOUT_​PCIE_​P/N[4:0]

Period

Period SSC On

9.849

10.201

ns

Period

Period SSC Off

9.849

10.151

ns

DtyCyc

Duty Cycle

40

60

%

V_​Swing

Differential Output Swing

300

—

mV

Slew_​rise

Rising Edge Rate

1.5

4

V/ns

Slew_​fall

Falling Edge Rate

1.5

4

V/ns

Jitter

—

150

ps

8, 9, 10

SSC

Spread Spectrum

0

0.5

%

11

SMBus/SMLink Clock (SMBCLK, SML0CLK)

fsmb

Operating Frequency

10

100

kHz

t18

High Time

4

50

µs

2

t19

Low Time

4.7

—

µs

t20

Rise Time

—

1000

ns

t21

Fall Time

—

300

ns

SMLink[1,0] (SML0CLK) (Fast Mode: Refer note 15)

fsmb

Operating Frequency

0

400

kHz

t18_​SMLFM

High Time

0.6

50

µs

2

t19_​SMLFM

Low Time

1.3

—

µs

t20_​SMLFM

Rise Time

—

300

ns

t21_​SMLFM

Fall Time

—

300

ns

SMLink[1,0] (SML0CLK) (Fast Mode Plus: Refer note 17)

fsmb

Operating Frequency

0

1000

kHz

t18_​SMLFMP

High Time

0.26

—

µs

2

t19_​SMLFMP

Low Time

0.5

—

µs

t20_​SMLFMP

Rise Time

—

120

ns

t21_​SMLFMP

Fall Time

—

120

ns

I²C Clock (Standard Mode)

fsmb

Operating Frequency

0

100

kHz

t18_​I2CSM

High Time

4

—

µs

2

t19_​I2CSM

Low Time

4.7

—

µs

t20_​I2CSM

Rise Time

—

1000

ns

t21_​I2CSM

Fall Time

—

300

ns

I²C Clock (Fast Mode)

fsmb

Operating Frequency

0

400

kHz

t18_​I2CFM

High Time

0.6

—

µs

2

t19_​I2CFM

Low Time

1.3

—

µs

t20_​I2CFM

Rise Time

20

300

ns

t21_​I2CFM

Fall Time

20 x (V_DD/5.5 V)

300

ns

I²C Clock (Fast Mode Plus)

fsmb

Operating Frequency

0

1

MHz

t18_​I2CFMP

High Time

0.26

—

µs

2

t19_​I2CFMP

Low Time

0.5

—

µs

t20_​I2CFMP

Rise Time

—

120

ns

t21_​I2CFMP

Fall Time

20 x (V_DD/5.5 V)

120

ns

I²C Clock (High Speed Mode, Maximum Bus Capacitance (C_B) = 100 pF)

fsmb

Operating Frequency

0

3.4

MHz

t18_​I2CHS1

High Time

60

—

ns

2

t19_​I2CHS1

Low Time

160

—

ns

t20_​I2CHS1

Rise Time

10

40

ns

t21_​I2CHS1

Fall Time

10

40

ns

I²C Clock (High Speed Mode, Maximum Bus Capacitance (C_B) = 400 pF)

fsmb

Operating Frequency

0

1.7

MHz

t18_​I2CHS2

High Time

120

—

ns

2

t19_​I2CHS2

Low Time

320

—

ns

t20_​I2CHS2

Rise Time

20

80

ns

t21_​I2CHS2

Fall Time

20

80

ns

HDA_​BLK (Intel® High Definition Audio)

f_HDA

Operating Frequency

24

—

MHz

Frequency Tolerance

—

100

ppm

t26a

Input Jitter (refer to Clock Chip Specification)

—

300

ppm

t27a

High Time (Measured at 0.75 Vcc)

18.75

22.91

ns

t28a

Low Time (Measured at 0.35 Vcc)

18.75

22.91

ns

Suspend Clock (PMC_​SUSCLK)

fsusclk

Operating Frequency

32

kHz

4

t39

High Time

9.5

—

µs

4

t39a

Low Time

9.5

—

µs

4

XTAL_​IN/XTAL_​OUT

ppm¹²

Crystal Tolerance cut accuracy maximum

35 ppm(@ 25 °C ±3 °C)

ppm¹²

Temp Stability Maximum

30 ppm(10 – 70 °C)

ppm¹²

Aging Maximum

5 ppm

Full-speed Source (Note 7)

t100

USBPx+, USBPx- Driver Rise Time

4

20

ns

1,6 CL = 50 pF

t101

USBPx+, USBPx- Driver Fall Time

4

20

ns

1,6 CL = 50 pF

t102

Source Differential Driver Jitter

- To Next Transition

- For Paired Transitions

–3.5

–4

3.5

4

ns

ns

2, 3

t103

Source SE0 interval of EOP

160

175

ns

4

t104

Source Jitter for Differential Transition to SE0 Transition

–2

5

ns

5

t105

Receiver Data Jitter Tolerance

- To Next Transition

- For Paired Transitions

–18.5

–9

18.5

9

ns

ns

3

t106

EOP Width: Receiver must accept EOP

82

—

ns

4

t107

Width of SE0 interval during differential transition

—

14

ns

Low-Speed Source (Note 8)

t108

USBPx+, USBPx – Driver Rise Time

75

300

ns

1,6

CL = 200 pF

CL = 600 pF

t109

USBPx+, USBPx – Driver Fall Time

75

300

ns

1,6

CL = 200 pF

CL = 600 pF

t110

Source Differential Driver Jitter

- To Next Transition

- For Paired Transitions

–25

–14

25

14

ns

ns

2,3

t111

Source SE0 interval of EOP

1.25

1.5

µs

4

t112

Source Jitter for Differential Transition to SE0 Transition

–40

100

ns

5

t113

Receiver Data Jitter Tolerance

- To Next Transition

- For Paired Transitions

–152

–200

152

200

ns

ns

3

t114

EOP Width: Receiver must accept EOP

670

—

ns

4

t115

Width of SE0 interval during differential transition

—

210

ns

UI

Unit Interval

199.94

200.06

99.97

100.03

ps

T_TX-EYE

Minimum Transmission Eye Width

0.625

—

0.646

—

UI

PU3

Polling Period U3 State

—

100

—

100

mS

PRX-Detect

Polling Period Rx Detect

—

100

—

100

mS

UI-3

Gen III Operating Data Period (6 Gb/s)

166.6083

166.6667

ps

t120gen3

Rise Time

0.2

0.48

UI

1

t121gen3

Fall Time

0.2

0.48

UI

2

t122

TX differential skew

—

20

ps

t123

COMRESET

304

336

ns

3

t124

COMWAKE transmit spacing

101.3

112

ns

3

t125

OOB Operating Data period

646.67

686.67

ns

4

t130_{100 kHz}

Bus Free Time Between Stop and Start Condition

4.7

—

µs

t131_{100 kHz}

Hold Time after (repeated) Start Condition. After this period, the first clock is generated.

4

—

µs

t132_{100 kHz}

Repeated Start Condition Setup Time

4.7

—

µs

t133_{100 kHz}

Stop Condition Setup Time

4

—

µs

t134_{100 kHz}

Data Hold Time

0

—

ns

t135_{100 kHz}

Data Setup Time

250

—

ns

t136

Device Time Out

25

35

ms

1

t137

Cumulative Clock Low Extend Time (slave device)

—

25

ms

2

t138

Cumulative Clock Low Extend Time (master device)

—

10

ms

3

T_por

Time in which a device must be operational after power-on reset

—

500

ms

t130_SM

Bus Free Time Between Stop and Start Condition

4.7

—

µs

t130_FM

Bus Free Time Between Stop and Start Condition

1.3

—

µs

t130_FMP

Bus Free Time Between Stop and Start Condition

0.5

—

µs

t131_SM

Hold Time after (repeated) Start Condition. After this period, the first clock is generated.

4

—

µs

t131_FM

Hold Time after (repeated) Start Condition. After this period, the first clock is generated.

0.6

—

µs

t131_FMP

Hold Time after (repeated) Start Condition. After this period, the first clock is generated.

0.26

—

µs

t131_HSM

Hold Time after (repeated) Start Condition. After this period, the first clock is generated.

160

—

ns

t132_SM

Repeated Start Condition Setup Time

4.7

—

µs

t132_FM

Repeated Start Condition Setup Time

0.6

—

µs

t132_FMP

Repeated Start Condition Setup Time

0.26

—

µs

t132_HSM

Repeated Start Condition Setup Time

160

—

ns

t133_SM

Stop Condition Setup Time

4

—

µs

t133_FM

Stop Condition Setup Time

0.6

—

µs

t133_FMP

Stop Condition Setup Time

0.26

—

µs

t133_HSM

Stop Condition Setup Time

160

—

ns

t134_SM

Data Hold Time

300

—

ns

1

t134_FM

Data Hold Time

0

—

ns

t134_FMP

Data Hold Time

0

—

ns

t135_SM

Data Setup Time

250

—

ns

t135_FM

Data Setup Time

100

—

ns

t135_FMP

Data Setup Time

50

—

ns

t135_HSM

Data Setup Time

10

—

ns

t143

Time duration for which HDA_​SDO is valid before HDA_​BCLK edge.

6.40

13.20(24 MHz)

40.00(12 MHz)

ns

t144

Time duration for which HDA_​SDO is valid after HDA_​BCLK edge.

6.40

13.20(24 MHz)

40.00(12 MHz)

ns

t145

Setup time for HDA_​SDI[1:0] at rising edge of HDA_​BCLK

20(24 MHz)

80(12 MHz)

—

ns

t146

Hold time for HDA_​SDI[1:0] at rising edge of HDA_​BCLK

3

—

ns

DMIC_​DATA[0:1] Setup Time to DMIC_​CLK[0:1] Rising

20

—

ns

DMIC_​DATA[0:1] Hold Time from DMIC_​CLK[0:1] Rising

1

—

ns

t160

SERIRQ Setup Time to PCICLK Rising

7

—

ns

t161

SERIRQ Hold Time from PCICLK Rising

0

—

ns

t162

GPIO, USB Resume Pulse Width

2

—

RTCCLK

t163

SPKR Valid Delay from OSC Rising

—

200

ns

t180a

Serial Clock Frequency

16.8

17.48

MHz

1

t183a

Tco of SPI MOSI and SPI I/O with respect to serial clock falling edge at the host

-13

14

ns

t184a

Setup of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

35.0

—

ns

t185a

Hold of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

1.50

—

ns

t186a

Setup of SPI CS# assertion with respect to serial clock rising edge at the host

30

—

ns

t187a

Hold of SPI CS# assertion with respect to serial clock falling edge at the host

30

—

ns

t188a

SPI CLK High time

23.84

—

ns

t189a

SPI CLK Low time

31.84

—

ns

t180b

Serial Clock Frequency

29.4

30.6

MHz

1

t183b

Tco of SPI MOSI and SPI I/O with respect to serial clock falling edge at the host

-8

8

ns

t184b

Setup of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

18.0

—

ns

t185b

Hold of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

1.50

—

ns

t186b

Setup of SPI CS# assertion with respect to serial clock rising edge at the host

30

—

ns

t187b

Hold of SPI CS# assertion with respect to serial clock falling edge at the host

30

—

ns

t188b

SPI CLK High time

16

—

ns

t189b

SPI CLK Low time

16

—

ns

t180c

Serial Clock Frequency

47.04

48.96

MHz

1

t183c

Tco of SPI MOSI and SPI I/O with respect to serial clock falling edge at the host

-3

6.2

ns

t184c

Setup of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

7.0

—

ns

t185c

Hold of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

1.50

—

ns

t186c

Setup of SPI CS# assertion with respect to serial clock rising edge at the host

30

—

ns

t187c

Hold of SPI CS# assertion with respect to serial clock falling edge at the host

30

—

ns

t188c

SPI CLK High time

7.84

—

ns

 2, 3

t189c

SPI CLK Low time

11.84

—

ns

 2, 3

t180c

Serial Clock Frequency

58.8

61.2

MHz

1

t183c

Tco of SPI MOSI and SPI I/O with respect to serial clock falling edge at the host

-3

4.7

ns

t184c

Setup of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

5

—

ns

t185c

Hold of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

1.5

—

ns

t186c

Setup of SPI CS# assertion with respect to serial clock rising edge at the host

30

—

ns

t187c

Hold of SPI CS# assertion with respect to serial clock falling edge at the host

30

—

ns

t188c

SPI CLK High time

5.67

—

ns

 2, 3

t189c

SPI CLK Low time

10.67

—

ns

 2, 3

F

Serial Clock Frequency

—

25

MHz

t183

Tco of SPI MOSI with respect to serial clock falling edge

-15

7.6

ns

t184

Setup of SPI MISO and SPI I/O with respect to serial clock rising edge

3.8

—

ns

t185

Hold of SPI MISO and SPI I/O with respect to serial clock rising edge

20

—

ns

t186

Setup of SPI CS# assertion with respect to serial clock rising edge

20

—

ns

t187

Hold of SPI CS# assertion with respect to serial clock falling edge

20

—

ns

F

Operating Frequency

—

6.25

Mbps

Slew_​rise

Output Rise Slope

1.452

2.388

V/ns

Slew_​fall

Output Fall Slope

1.552

2.531

V/ns

FI2S

Clock Frequency

—

12.288

MHz

FI2S

Clock Frequency

—

9.6

MHz

SFRM

TCO

Clock to Output Delay

—8

15

ns

TSU

Setup Time

40

—

ns

THD

Hold Time

1

—

ns

TXD

TCO

Clock to Output Delay

—8

15

ns

SCLK

F_I2S

Clock Frequency

—

12.288

MHz

SFRM

T_SU

Setup Time

9

—

ns

T_HD

Hold Time

10

—

ns

RXD

T_SU

Setup Time

9

—

ns

T_HD

Hold Time

10

—

ns

TXD

T_CO

Clock to Output Delay

0

21

ns

SCLK

F_I2S

Clock Frequency

—

9.6

MHz

SFRM

T_SU

Setup Time

15

—

ns

T_HD

Hold Time

10

—

ns

RXD

T_SU

Setup Time

15

—

ns

T_HD

Hold Time

10

—

ns

TXD

T_CO

Clock to Output Delay

0

28

ns

t180c

Serial Clock Frequency

29.4

30.6

MHz

1

t183c

Tco of SPI MOSI and SPI I/O with respect to serial clock falling edge at the host

-9

8

ns

t184c

Setup of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

17

—

ns

t185c

Hold of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

1.3

—

ns

t186c

Setup of SPI CS# assertion with respect to serial clock rising edge at the host

30

—

ns

t187c

Hold of SPI CS# assertion with respect to serial clock falling edge at the host

30

—

ns

t188c

SPI CLK High time

16

—

ns

 2, 3

t189c

SPI CLK Low time

16

—

ns

 2, 3

t180c

Serial Clock Frequency

58.8

61.2

MHz

1

t183c

Tco of SPI MOSI and SPI I/O with respect to serial clock falling edge at the host

-3

2.5

ns

t184c

Setup of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

5.5

—

ns

t185c

Hold of SPI MISO and SPI I/O with respect to serial clock falling edge at the host

1.3

—

ns

t186c

Setup of SPI CS# assertion with respect to serial clock rising edge at the host

30

—

ns

t187c

Hold of SPI CS# assertion with respect to serial clock falling edge at the host

30

—

ns

t188c

SPI CLK High time

8

—

ns

 2, 3

t189c

SPI CLK Low time

8

—

ns

 2, 3

FCLK

Clock Frequency

200

MHz

typical Value

TX Slew rate

TX pad Slew rate

1.125

V/ns

Test Load @30pF

TCO (HS400 DATA)

Tx Rising/Falling Clock to Data Output Delay (HS400)

-0.65

1.82

ns

1

TCO (HS200 DATA)

Tx Rising Clock to Data Output Delay (HS200)

-0.66

2.356

ns

1

TCO (DDR50 DATA)

Tx Rising/Falling Clock to Data Output Delay (DDR50)

2.5

-

ns

1

TCO (SDR50 DATA)

Tx Rising Clock to Data Output Delay (SDR50)

3

-

ns

1

TCO (DS DATA)

Tx Falling Clock to CMD Output Delay (DS)

-4.673

5.480862

ns

1

TCO (HS400 CMD)

Tx Rising/Falling Clock to CMD Output Delay (HS400)

0.8

-

ns

1

TCO (HS200 CMD)

Tx Rising Clock to CMD Output Delay (HS200)

0.8

-

ns

1

TCO (DDR50 CMD)

Tx Rising/Falling Clock to CMD Output Delay (DDR50)

3

-

ns

1

TCO (SDR50 CMD)

Tx Rising Clock to CMD Output Delay (SDR50)

3

-

ns

1

TCO (DS CMD)

Tx Falling Clock to CMD Output Delay (DS)

3

-

ns

1

TDVW (HS200)

Rx Data Valid Window time to CLK Rising Edge

-1.808

ns

TSu (DDR50 DATA)

Rx Data Setup Time to CLK Rising/Falling Edge (DDR50)

-3.635

ns

TH (DDR50 DATA)

Rx Data Hold Time to CLK Rising/Falling Edge (DDR50)

4.318

ns

TSu (SDR50 DATA)

Rx Data Setup Time to CLK Rising/Falling Edge (SDR50)

-3.751

ns

TH (SDR50 DATA)

Rx Data Hold Time to CLK Rising/Falling Edge (SDR50)

4.367

ns

TSu (DS DATA)

Rx Data Setup Time to CLK Rising/Falling Edge (DS)

0.9399

ns

TH (DS DATA)

Rx Data Hold Time to CLK Rising/Falling Edge (DS)

-4.593

ns

TWC(DDR50)

CLK Cycle Time (DDR50 Mode)

20

ns

TWC(SDR50)

CLK Cycle Time (SDR50 Mode)

20

ns

TWC(DS)

CLK Cycle Time (DS Mode)

40

ns

TDVW (HS400)

Rx Data Valid wondow to CLK Rising/Falling Edge (HS400)

2.37

ns

TSu (DDR50 CMD)

Rx CMD Setup Time to CLK Rising/Falling Edge (DDR50)

1.056

ns

TH (DDR50 CMD)

Rx CMD Hold Time to CLK Rising/Falling Edge (DDR50)

2.938

ns

TSu (SDR50 CMD)

Rx CMD Setup Time to CLK Rising/Falling Edge (SDR50)

-3.751

ns

TH (SDR50 CMD)

Rx CMD Hold Time to CLK Rising/Falling Edge (SDR50)

4.367

ns

TSu (DS CMD)

Rx CMD Setup Time to CLK Rising/Falling Edge (DS)

-2.80209

ns

TH (DS CMD)

Rx CMD Hold Time to CLK Rising/Falling Edge (DS)

-2.366

ns

TWC (HS200)

CLK Cycle Time (HS200 Mode)

5

ns

TWC (HS400)

CLK Cycle Time (HS400 Mode)

5

ns

TWC(DDR50)

CLK Cycle Time (DDR50 Mode)

20

ns

TWC(SDR50)

CLK Cycle Time (SDR50 Mode)

20

ns

TWC(DS)

CLK Cycle Time (DS Mode)

40

ns