PCIe* Device Reference Clock Request Mapping 1 (DRCRM1) – Offset 100 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
- DEVIDLE Control (HECI1_DEVIDLEC)
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
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Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
- Power Management Control (PMCTL)
Keyboard and Text (KT) Additional Configuration
- Power Management Control and Status (KT_CSXE_PMD_PMCSRBSE_PMCSR)
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
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SATA Configuration
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SATA MXTBA
SDXC (SD Card) PCR
- Dynamic Clock Gating Control (GPPRVRW1)
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

PCIe* Device Reference Clock Request Mapping 1 (DRCRM1) – Offset 100

Bit Range	Default	Access	Field Name and Description
30	-	-	Reserved
29:25	00101b	RW/L	PCIe Express Port 6 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 6.
24:20	00100b	RW/L	PCI Express Port 5 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 5.
19:15	00011b	RW/L	PCI Express Port 4 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 4.
14:10	00010b	RW/L	PCI Express Port 3 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 3.
9:5	00001b	RW/L	PCI Express Port 2 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 2.
4:0	00000b	RW/L	PCI Express Port 1 CLKREQ Mapping () The mapping of PCIe Port 1 to the corresponding CLKREQ# pin is configured by this field. 00h: Port 1 maps to CLKREQ0# pin. 01h: Port 1 maps to CLKREQ1# pin. ... 05h: Port 1 maps to CLKREQ5# pin. Others: Reserved Software must never map multiple PCIe Ports to the same CLKREQ# pin. The hardware behavior is undefined if this ever happens. Note:This field must be configured prior to enabling any power management features. Note: Configuring this field to map to any unsupported CLKREQ# pins may result in undefined hardware behavior. This register bit is Read-Only when the CC.SRL bit is set. Register Attribute: Static.

PCIe* Device Reference Clock Request Mapping 2 (DRCRM2)

Common Control (CC) PCIe* Device Reference Clock Request Mapping 2 (DRCRM2)