Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Clock Control (clockcontrol) – Offset 2c
This register is used to program the Clock frequency select, generator select, Clock enable,Internal Clock state fields.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:8 | 00h | RW | SDCLK Frequency Select (clkctrl_sdclkfreqsel) This register is used to select the frequency of the clock pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency in the capabilities register. Only the following settings are allowed. |
7:6 | 0h | RW | Upper Bits of SDCLK Frequency Select (clkctrl_sdclkfreqsel_upperbits) Bit 07-06 is assigned to bit 09-08 of clock divider inSDCLK Frequency Select. |
5 | 0h | RW | Clock Generator Select (clkctrl_clkgensel) This bit is used to select the clock generator mode inSDCLK Frequency Select.If the Programmable Clock Mode is supported (non-zerovalue is set to Clock Multiplier in the Capabilitiesregister), this bit attribute is RW, and if not supported,this bit attribute is RO and zero is read.This bit depends on the setting of Preset Value Enable in the Host Control 2 register. If the Preset Value Enable = 0, this bit is set by HostDriver. If the Preset Value Enable = 1, this bit is automatically set to a value specified in one of Preset Value registers. |
4:3 | - | - | Reserved
|
2 | 0h | RW | SD Clock Enable (clkctrl_sdclkena) The HC shall stop SDCLK when writing this bit to 0.SDCLK frequency Select can be changed when this bit is0. |
1 | 0h | RO | Internal Clock Stable (sdhcclkgen_intclkstable_dsync) This bit is set to 1 when SD clock is stable after writingto Internal Clock Enable in this register to 1. The SDHost Driver shall wait to set SD Clock Enable until this bit is set to 1. |
0 | 0h | RW | Internal Clock Enable (clkctrl_intclkena) This bit is set to 0 when the HD is not using the HC orthe HC awaits a wakeup event. The HC should stop itsinternal clock to go very low power state.1 - Oscillate |