Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
D0I3_MAX_POW_LAT_PG_CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset a0
DEVICE PG CONFIG
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:22 | - | - | Reserved
|
21 | 0b | RW | Hardware Autonomous Enable (HAE) If set, then the PGCB may request a PG whenever it is idle. |
20 | - | - | Reserved
|
19 | 0b | RW | Sleep Enable (SLEEP_EN) If clear, then IP will never asset Sleep to the retention flops. If set, then IP may assert Sleep during PG'ing. |
18 | 0b | RW | PG Enable (PGE) If clear, then IP will never request a PG. If set, then IP may request PG when proper conditions are met. |
17 | 0b | RW | D3-Hot Enable (I3_ENABLE) If 1, then function will power gate when idle and the POWERSTATE bits in the function = 11(D3). |
16 | 0b | RW | PMC Request Enable (PMCRE) If this bit is set to '1', the function will power gate when idle. |
15:13 | - | - | Reserved
|
12:10 | 2h | RW/O | Power On Latency Scale (POW_LAT_SCALE) This value is written by BIOS to communicate to the driver. |
9:0 | 000h | RW/O | Power On Latency Value (POW_LAT_VALUE) This value is written by BIOS to communicate to the driver. |