Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
eSPI Slave Configuration Register And Link Control (SLV_CFG_REG_CTL) – Offset 4000
Along with SLV_CFG_REG_DATA, this register controls Rd/Wr access to Slave Configuration registers using eSPI Get/Set_Configuration, Get_Status and In-Band Reset cycles. It allows Tunneled Access to Slave Configuration (TASC) registers from Host/ME software/firmware.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW/1S/V | Slave Configuration Register Access Enable (SCRE) Writing a 1 to this field triggers an access (SCRT) to a Slave Config Register ('Go'). |
30:28 | 0b | RW/1C/V | Slave Configuration Register Access Status (SCRS) This field is set by upon thecompletion of a configuration register access (SCRE). Software must clear this field bywriting all 1s before initiating another Slave configuration register access (SCRE). |
27 | 0b | RW/1S | IOSF-SB eSPI Link Configuration Lock (SBLCL) When set, eSPI controller prevents writes (i.e.,SET_CONFIGURATION)to any eSPI Specificationdefined Slave Capabilities and Configuration registers in the reserved register addressrange (0h – 7FFh). Access to Slave implementation specific configuration registersoutside this range are not impacted by this lock bit and are always available – accessprotections to such registers are Slave implementation dependent. |
26:21 | - | - | Reserved
|
20:19 | 0b | RW | Slave ID (SID) eSPI Slave ID (CS#) to which the Slave Configuration Register Access (SCRT) is directed. |
18 | - | - | Reserved
|
17:16 | 0b | RW | Slave Configuration Register Access Type (SCRT) 00: Slave Configuration register read from address SCRA[11:0] (GET_CONFIG |
15:12 | - | - | Reserved
|
11:0 | 0h | RW | Slave Configuration Register Address (SCRA) Per eSPI Spec / eSPI Compatibility Spec. |