Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
General Interrupt Status Register (GEN_INT_STS) – Offset fed00020
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
62:8 | - | - | Reserved
|
7 | 0b | RW/1C | Timer 7 Interrupt Active (T07_INT_STS) Same functionality as Timer 0. |
6 | 0b | RW/1C | Timer 6 Interrupt Active (T06_INT_STS) Same functionality as Timer 0. |
5 | 0b | RW/1C | Timer 5 Interrupt Active (T05_INT_STS) Same functionality as Timer 0. |
4 | 0b | RW/1C | Timer 4 Interrupt Active (T04_INT_STS) Same functionality as Timer 0. |
3 | 0b | RW/1C | Timer 3 Interrupt Active (T03_INT_STS) Same functionality as Timer 0. |
2 | 0b | RW/1C | Timer 2 Interrupt Active (T02_INT_STS) Same functionality as Timer 0. |
1 | 0b | RW/1C | Timer 1 Interrupt Active (T01_INT_STS) Same functionality as Timer 0. |
0 | 0b | RW/1C | Timer 0 Interrupt Active (T00_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer.(default = 0) |