Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0) – Offset 140
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_23) Applied to GPP_A23. Same description as bit 0. |
22 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_22) Applied to GPP_A22. Same description as bit 0. |
21 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_21) Applied to GPP_A21. Same description as bit 0. |
20 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_20) Applied to GPP_A20. Same description as bit 0. |
19 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_19) Applied to GPP_A19. Same description as bit 0. |
18 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_18) Applied to GPP_A18. Same description as bit 0. |
17 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_17) Applied to GPP_A17. Same description as bit 0. |
16 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_16) Applied to GPP_A16. Same description as bit 0. |
15 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_15) Applied to GPP_A15. Same description as bit 0. |
14 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_14) Applied to GPP_A14. Same description as bit 0. |
13 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_13) Applied to GPP_A13. Same description as bit 0. |
12 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_12) Applied to GPP_A12. Same description as bit 0. |
11 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_11) Applied to GPP_A11. Same description as bit 0. |
10 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_10) Applied to GPP_A10. Same description as bit 0. |
9 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_9) Applied to GPP_A9. Same description as bit 0. |
8 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_8) Applied to GPP_A8. Same description as bit 0. |
7 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_7) Applied to GPP_A7. Same description as bit 0. |
6 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_6) Applied to GPP_A6. Same description as bit 0. |
5 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_5) Applied to GPP_A5. Same description as bit 0. |
4 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_4) Applied to GPP_A4. Same description as bit 0. |
3 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_3) Applied to GPP_A3. Same description as bit 0. |
2 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_2) Applied to GPP_A2. Same description as bit 0. |
1 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_1) Applied to GPP_A1. Same description as bit 0. |
0 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_A_0) These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). |