Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA) – Offset 9c
NOTE: This register applies to the following input and output streams at the corresponding offsets:
Input stream 0: offset 9Ch
Input stream 1: offset BCh
Input stream 2: offset DCh
Input stream 3: offset FCh
Input stream 4: offset 11Ch
Input stream 5: offset 13Ch
Input stream 6: offset 15Ch
Input stream 7: offset 29Ch
Input stream 8: offset 2BCh
Input stream 9: offset 2DCh
Input stream 10: offset 2FCh
Input stream 11: offset 31Ch
Input stream 12: offset 33Ch
Input stream 13: offset 35Ch
Input stream 14: offset 37Ch
Output stream 0: offset 17Ch
Output stream 1: offset 19Ch
Output stream 2: offset 1BCh
Output stream 3: offset 1DCh
Output stream 4: offset 1FCh
Output stream 5: offset 21Ch
Output stream 6: offset 23Ch
output stream 7: offset 25Ch
Output stream 8: offset 27Ch
Output stream 9: offset 39Ch
Output stream 10: offset 3BCh
Output stream 11: offset 3DCh
Output stream 12: offset 4FCh
Output stream 13: offset 41Ch
Output stream 14: offset 43Ch
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:0 | 00000000h | RW/L | Buffer Descriptor List Upper Base Address (BDLPUBA) Upper 32bit address of the Buffer Descriptor List. This value should only |