LPC I/O Decode Range (LPCIOD) – Offset 2770 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
- DEVIDLE Control (HECI1_DEVIDLEC)
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
- Function Configuration (FNCFG)
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
- Power Management Control (PMCTL)
Keyboard and Text (KT) Additional Configuration
- Power Management Control and Status (KT_CSXE_PMD_PMCSRBSE_PMCSR)
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
SATA MXTBA
SDXC (SD Card) PCR
- Dynamic Clock Gating Control (GPPRVRW1)
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

LPC I/O Decode Range (LPCIOD) – Offset 2770

Offset 2770h: LPCIOD LPC I/O Decode Ranges

Bit Range	Default	Access	Field Name and Description
30:13	-	-	Reserved
12	0b	RW/L	FDD Range (FDD) The following table describes which range to decode for the FDD Port. Bits Decode Range 0 3F0h – 3F5h, 3F7h (Primary) 1 370h – 375h, 377h (Secondary) This register is Read-Only if the DMIC.SRL field is set.
11:10	-	-	Reserved
9:8	00b	RW/L	LPT Range (LPT) The following table describes which range to decode for the LPT Port. Bits Decode Range 00 378h - 37Fh and 778h – 77Fh 01 278h – 27Fh (port 279h is read only) and 678h – 67Fh 10 3BCh – 3BEh and 7BCh – 7BEh 11 Reserved This register is Read-Only if the DMIC.SRL field is set.
7	-	-	Reserved
6:4	000b	RW/L	ComB Range (CB) The following table describes which range to decode for the COMB Port. Bits Decode Range 000 3F8h – 3FFh (COM1) 001 2F8h – 2FFh (COM2) 010 220h – 227h 011 228h – 22Fh 100 238h – 23Fh 101 2E8h – 2EFh (COM 4) 110 338h – 33Fh 111 3E8h – 3EFh (COM 3) This register is Read-Only if the DMIC.SRL field is set.
3	-	-	Reserved
2:0	000b	RW/L	ComA Range (CA) The following table describes which range to decode for the COMA Port. Bits Decode Range 000 3F8h – 3FFh (COM1) 001 2F8h – 2FFh (COM2) 010 220h – 227h 011 228h – 22Fh 100 238h – 23Fh 101 2E8h – 2EFh (COM 4) 110 338h – 33Fh 111 3E8h – 3EFh (COM 3) This register is Read-Only if the DMIC.SRL field is set.

LPC I/O Enable (LPCIOE)

I/O Trap Register 1 high (IOT1_HIGH) LPC I/O Enable (LPCIOE)