Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Message Signaled Interrupt Message Control (MSI_MCTL) – Offset 82
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14:9 | - | - | Reserved
|
8 | 0b | RO | Per-Vector Masking Capable (PVM) Specifies whether controller supports MSI per vector masking. Not supported |
7 | 1b | RO | 64 Bit Address Capable (C64) Specifies whether capable of generating 64-bit messages. This device is 64-bit capable. |
6:4 | 0h | RW | Multiple Message Enable (MME) Indicates the number of messages the controller should assert. This device supports multiple message MSI. |
3:1 | 011b | RO | Multiple Message Capable (MMC) Indicates the number of messages the controller wishes to assert.This field must be set by HW to reflect the number of Interrupters supported. |
0 | 0b | RW | MSI Enable (MSIE) If set to 1, MSI is enabled and the traditional interrupt pins are not used to generate interrupts. |