Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Miscellaneous Port Configuration (MPC) – Offset d8
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW | Power Management SCI Enable (PMCE) 0 = SCI generation based on a power management event is disabled. |
30 | 0b | RW | Hot Plug SCI Enable (HPCE) 0 = SCI generation based on a hot-plug event is disabled. |
29 | 0b | RW/L | Link Hold Off (LHO) When set, the port will not take any TLP. This is used during loopback mode to fill up the downstream queue. |
28 | 0b | RW/L | Address Translater Enable (ATE) Used to enable address translation via the AT bits in this register during loopback mode. |
27 | - | - | Reserved
|
26 | 0b | RW/L | Port8xh Decode Enable (P8XDE) When set, allows PCIe Root Port to claim I/O cycles within the range from 80h - 8Fh inclusive and forwarding the cycle to the link. |
25 | 0b | RW/L | Invalid Receive Range Check Enable (IRRCE) When set, the receive transaction layer will treat the TLP as an Unsupported Request error if the address range of a Memory request does not fall outside the range between prefetchable and non-prefetchable base and limit. |
24 | 1b | RW/L | BME Receive Check Enable (BMERCE) When set, the receive transaction layer will treat the TLP as an Unsupported Request error if a memory or I/O read or write request is received and the Bus Master Enable bit is not set. |
23 | 0b | RW/O | Secured Register Lock (SRL) When this bit is set, all the secured registers will be locked and will be Read-Only. |
22 | 0b | RW/L | Detect Override (FORCEDET) 0: Normal operation. Detect output from AFE is sampled for presence detection. |
21 | 0b | RW | Flow Control During L1 Entry (FCDL1E) br]0: No flow control update DLLPs sent during L1 Ack transmission |
20:18 | 100b | RW | Unique Clock Exit Latency (UCEL) This value represents the L0s Exit Latency for unique-clock configurations (LCTL.CCC = '0). It defaults to 512ns to less than 1s, but may be overridden by BIOS. |
17:15 | 010b | RW | Common Clock Exit Latency (CCEL) This value represents the L0s Exit Latency for common-clock configurations (LCTL.CCC = '1). It defaults to 128ns to less than 256ns, but may be overridden by BIOS. |
14:13 | 00b | RW | PCIe MEx Speed Disable (PCIEMEXSD) When operating as PCI Express: |
12:8 | - | - | Reserved
|
7 | 0b | RW | Port I/OxApic Enable (PAE) When set, a range is opened through the bridge for the following memory addresses: |
6:3 | - | - | Reserved
|
2 | 0b | RW/O | Bridge Type (BT) This register can be used to modify the Base Class and Header Type fields from the default PCI-to-PCI bridge to a Host Bridge. Having the root port appear as a Host Bridge is useful in some server configurations. |
1 | 0b | RW | Hot Plug SMI Enable (HPME) 0 = SMI generation based on a hot-plug event is disabled. |
0 | 0b | RW | Power Management SMI Enable (PMME) 0 = SMI generation based on a power management event is disabled. |