Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Normal Interrupt Status Enable (normalintrstsena) – Offset 34
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14:10 | - | - | Reserved
|
9 | 0h | RW | INT_A Status Enable (int_a_stsena) If this bit is set to 0, the Host Controller shall clear theinterrupt request to the System. The Host Driver mayclear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts. |
8 | 0h | RW | Card Interrupt Status Enable (sdhcregset_cardintstsena) If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is setto 1. |
7 | 0h | RW | Card Removal Status Enable (sdhcregset_cardremstsena) This status is set if the Card Inserted in the PresentState register changes from 1 to 0. |
6 | 0h | RW | Card Insertion Status Enable (sdhcregset_cardinsstsena) This status is set if the Card Inserted in the PresentState register changes from 0 to 1. |
5 | 0h | RW | Buffer Read Ready Status Enable (buffrd_readtstsena) This status is set if the Buffer Read Enable changes from 0 to 1. |
4 | 0h | RW | Buffer Write Ready Status Enable (buffwr_readtstsena) This status is set if the Buffer Write Enable changesfrom 0 to 1. |
3 | 0h | RW | DMA Interrupt Status Enable (dmaintrstsena) This status is set if the HC detects the Host DMA BufferBoundary in the Block Size register. |
2 | 0h | RW | Block Gap Event Status Enable (blockgap_eventstsena) If the Stop At Block Gap Request in the BlockGap Control Register is set, this bit is set. |
1 | 0h | RW | Transfer Complete Status Enable (xfrcmpltstsena) This bit is set when a read / write transaction iscompleted. |
0 | 0h | RW | Command Complete Status Enable (cmdcmpltstsena) This bit is set when we get the end bit of the commandresponse. |