Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
PCI Express Replay Timer Policy 2 (PCIERTP2) – Offset 304
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 00b | RW | Lane 0 Lane Number (L0LN) Lane 0 Lane Number(L0LN): This field specifies the lane number to be used in the per-lane GEN3 scrambling/descrambling logic for lane 0 when entering Loopback from Configuration state, prior to Link width negotiation and for GEN3 Polling Compliance entry where the lane number is not available. |
29:28 | 01b | RW | Lane 1 Lane Number (L1LN) Lane 1 Lane Number(L1LN): This field specifies the lane number to be used in the per-lane GEN3 scrambling/descrambling logic for lane 1 when entering Loopback from Configuration state, prior to Link width negotiation and for GEN3 Polling Compliance entry where the lane number is not available. |
27:26 | 10b | RW | Lane 2 Lane Number (L2LN) Lane 2 Lane Number(L2LN): This field specifies the lane number to be used in the per-lane GEN3 scrambling/descrambling logic for lane 2 when entering Loopback from Configuration state, prior to Link width negotiation and for GEN3 Polling Compliance entry where the lane number is not available. |
25:24 | 11b | RW | Lane 3 Lane Number (L3LN) Lane 3 Lane Number(L3LN): This field specifies the lane number to be used in the per-lane GEN3 scrambling/descrambling logic for lane 3 when entering Loopback from Configuration state, prior to Link width negotiation and for GEN3 Polling Compliance entry where the lane number is not available. |
23 | 1b | RW | Loopback Master EQ TS1 Enable (LMEQTS1E) Loopback Master EQ TS1 Enable(LMEQTS1E): When set, the Loopback Master will use EQ TS1 Ordered Sets to direct the Loopback Slave into Loopback from Configuration.Linkwidth.Start. The Preset field of the EQ TS1 Ordered Sets will be specified by Upstream Port Lane X Transmitter Preset and Upstream Port Lane X Receiver Preset Hint fields in the Lane Equalization Control registers. |
22 | 1b | RW | Loopback Master EQ Change Enable (LMEQCE) Loopback Master EQ Change Enable(LMEQCE): This field is applicable to the case where Loopback is entered from Recovery state. When set, the Loopback Master will set the EC field of the GEN3 TS1 Ordered Sets to the appropriate value based on the ports direction(10b or 11b) to direct the Loopback Slave into Loopback from Recovery state. The Preset field of the GEN3 TS1 Ordered Sets will be specified by Upstream Port Lane X Transmitter Preset and Upstream Port Lane X Receiver Preset Hint fields in the Lane Equalization Control registers. |
21:12 | - | - | Reserved
|
11:8 | Bh | RW | Gen 3 x1 (G3X1) Gen 3 x1 (G3X1): Determines how many link clock cycles the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. |
7:4 | 8h | RW | Gen 3 x2 (G3X2) Gen 3 x2 (G3X2): Determines how many link clock cycles the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. |
3:0 | 6h | RW | Gen 3 x4 (G3X4) Gen 3 x4 (G3X4): Determines how many link clock cycles the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. |