Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
PMC Memory Mapped Registers
The PMC memory mapped registers are accessed based upon offsets from PM Base Address (PWRMBASE) defined in PCI Device 31: Function 2.
Offset | Size (Bytes) | Register Name (Register Symbol) | Default Value |
---|---|---|---|
1910h | 4 | 0h | |
1914h | 4 | 0h | |
1920h | 4 | 432h | |
1924h | 4 | 0h | |
1928h | 4 | 0h | |
192ch | 4 | 0h | |
1020h | 4 | 20014000h | |
1024h | 4 | 4h | |
1030h | 4 | 0h | |
1048h | 4 | 0h | |
104ch | 4 | 0h | |
1050h | 4 | 0h | |
1054h | 4 | 0h | |
1930h | 4 | 0h | |
1934h | 4 | 0h | |
1938h | 4 | 0h | |
193ch | 4 | 0h | |
1940h | 4 | 0h | |
1b24h | 4 | 0h | |
1b28h | 4 | 0h | |
10b0h | 4 | 0h | |
10c0h | 4 | 0h | |
10c4h | 4 | FFFFh | |
10c8h | 4 | 0h | |
10cch | 4 | 0h | |
10d0h | 4 | HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5) | 0h |
1b40h | 4 | 0h | |
1b44h | 4 | 0h | |
1ba8h | 4 | 0h | |
1bach | 4 | 0h | |
1bb0h | 4 | 0h | |
1bb4h | 4 | 0h | |
1bd4h | 4 | 0h | |
1bd8h | 4 | 0h | |
1be0h | 4 | 0h | |
1be8h | 4 | 0h | |
1bech | 4 | 0h | |
1d00h | 4 | 0h | |
1d04h | 4 | 0h | |
1d08h | 4 | 0h | |
1d0ch | 4 | 0h | |
1d10h | 4 | 0h | |
1d14h | 4 | 0h | |
1d18h | 4 | 0h | |
1d1ch | 4 | 0h | |
1d20h | 4 | 0h | |
1d24h | 4 | 0h | |
1d28h | 4 | 0h | |
1d2ch | 4 | 0h | |
1d30h | 4 | 0h | |
1d34h | 4 | 0h | |
1d38h | 4 | 0h | |
1d3ch | 4 | 0h | |
1d80h | 4 | 0h | |
1d84h | 4 | 0h | |
1d90h | 4 | 0h | |
1d94h | 4 | 0h | |
1da0h | 4 | 6000606h | |
1db0h | 4 | 0h | |
1dd0h | 4 | 0h | |
1de0h | 4 | 0h | |
1de4h | 4 | 0h | |
1e20h | 4 | 0h | |
1e24h | 4 | 0h | |
1e28h | 4 | Non-Static PG Related Function Disable Register 1 (NST_PG_FDIS_1) | 0h |
1200h | 4 | 0h | |
1204h | 4 | 0h | |
1210h | 4 | 0h | |
1220h | 4 | 0h | |
1224h | 4 | 0h | |
1228h | 4 | Timed GPIO0 periodic Interval Value 31_0 (TGPIOPIV0_31_0) | 0h |
122ch | 4 | Timed GPIO 0 periodic Interval Value 63_32 (TGPIOPIV0_63_32) | 0h |
1230h | 4 | 0h | |
1234h | 4 | Timed GPIO0 Time Capture register 63_32 (TGPIOTCV0_63_32) | 0h |
1238h | 4 | Timed GPIO0 Event Counter Capture register 31_0 (TGPIOECCV0_31_0) | 0h |
123ch | 4 | Timed GPIO0 Event Counter Capture register 63_32 (TGPIOECCV0_63_32) | 0h |
1240h | 4 | 0h | |
1244h | 4 | Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32) | 0h |
1310h | 4 | 0h | |
1320h | 4 | 0h | |
1324h | 4 | 0h | |
1328h | 4 | Timed GPIO1 periodic Interval Value 31_0 (TGPIOPIV1_31_0) | 0h |
132ch | 4 | Timed GPIO 1 periodic Interval Value 63_32 (TGPIOPIV1_63_32) | 0h |
1330h | 4 | 0h | |
1334h | 4 | 0h | |
1338h | 4 | Timed GPIO0 Event Counter Capture register 31_0 (TGPIOECCV1_31_0) | 0h |
133ch | 4 | Timed GPIO0 Event Counter Capture register 63_32 (TGPIOECCV1_63_32) | 0h |
1340h | 4 | 0h | |
1344h | 4 | 0h | |
1670h | 4 | 0h | |
1800h | 4 | FFFFFFFFh | |
1804h | 4 | FFFFFFFFh | |
1808h | 4 | FFFFFFFFh | |
180ch | 4 | FFFFFFFFh | |
1810h | 4 | 0h | |
1818h | 4 | 20h | |
1824h | 4 | 0h | |
1828h | 4 | 0h | |
182ch | 4 | 0h | |
1830h | 4 | 0h | |
1834h | 4 | 0h | |
183ch | 4 | 0h | |
1848h | 4 | 0h | |
184ch | 4 | 0h | |
1850h | 4 | 0h | |
1854h | 4 | 0h | |
1858h | 4 | 0h | |
1868h | 4 | 0h | |
1880h | 4 | 0h | |
1884h | 4 | 0h | |
1888h | 4 | 0h | |
188ch | 4 | 0h | |
1898h | 4 | 0h | |
18a8h | 4 | 0h | |
18ach | 4 | 0h | |
18b0h | 4 | 0h | |
18b4h | 4 | 0h | |
18c0h | 4 | 0h | |
18c4h | 4 | PMSYNC Thermal Power Reporting Configuration (PMSYNC_TPR_CFG) | 0h |
18c8h | 4 | 0h | |
18d0h | 4 | 0h | |
18d4h | 4 | 0h | |
18e0h | 4 | 0h | |
18e4h | 4 | 0h | |
18e8h | 4 | 8000h | |
18ech | 4 | 0h | |
18fch | 4 | 0h | |
1e40h | 4 | 0h | |
1e44h | 4 | 0h | |
10b4h | 4 | 0h | |
10b8h | 4 | 0h | |
10bch | 4 | 0h | |
1900h | 4 | 1000h |