Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Power Management Control (PMCTRL_REG) – Offset 80a4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW | Async PME Source Enable (ASYNC_PME_SRC_EN) This field allows the async PME source to be allowed to generate PME. |
30 | 0h | RW | Legacy PME Source Enable (LEGACY_PME_SRC_EN) This field allows the legacy PME source to be used in PME generation. |
29 | 0h | RW | Reset Warn Power Gate Trigger Disable (RESET_WARN_PWR_GATE_TRIGGER_DISABLE) This field controls the actions taken for due to reset warn. |
28 | 0h | RW | CLR_PME_FLAG_PULSE_AUX_CCLK (CLR_PME_FLAG_PULSE_AUX_CCLK) Internal PME flag Clear |
27 | 0h | RW | Disable RTD3 power gating when in D3 (DIS_D3_PG) Disable RTD3 power gating when in D3 and context save operation is not performed |
26 | 0h | RW | XLFPSCOUNTSRC (XLFPSCOUNTSRC) XLFPSCOUNTSRC (Source for LFPS OFF Counter) |
25 | 0h | RW | XELFPSRTC (XELFPSRTC) XELFPSRTC (Enable LFPS Filtering on RTC) |
24 | 0h | RW | XMPHYSPGDD0I2 (XMPHYSPGDD0I2) XMPHYSPGDD0I2 (ModPhy Sus Well Power Gate Disable for D0I2) |
23 | 0h | RW | XMPHYSPGDD0I3 (XMPHYSPGDD0I3) XMPHYSPGDD0I3 (ModPhy Sus Well Power Gate Disable for D0I3) |
22 | 0h | RW | XMPHYSPGDRTD3 (XMPHYSPGDRTD3) XMPHYSPGDRTD3 (ModPhy Sus Well Power Gate Disable for RTD3) |
21:18 | Bh | RW | XD3RTCPTTM (XD3RTCPTTM) XD3RTCPTTM (D3 RTC Port Timer Tick Multiplier) |
17 | 0h | RW | U3 LFPS Periodic Sampling ON Time Control (U3_LFPS_PRDC_SAMPLING_ON_TIME_CTRL) This field controls the ON time for the LFPS periodic sampling for USB3/SSIC ports. |
16 | 1h | RW | AON LFPS Detector Enable Mode (AON_LFPS_DETECTOR_EN_MODE) 1 - Allow the LFSP Detector in AON to own LFPS detection when the port is in PS3 for U2/U3 - not RxD regardless of port ownership. |
15:8 | FFh | RW | SS U3 LFPS Detection Threshold (SS_U3_LFPS_DETECTION_THRESHOLD) This field controls the threshold used to determine when a valid U3 Wake is detected through when using the unfiltered LFPS source. |
7:4 | 9h | RW | SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL (SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL) This field controls the OFF time for the LFPS periodic sampling for USB3 Ports |
3 | 0h | RW | PS3 LFPS Source Select (PS3_LFPS_SRC_SEL) 0 LFPS Source is unfiltered |
2 | 1h | RW | XHCI Engine Autonomous Power Gate Exit Reset Policy (XHC_AUTO_PWRGATE_EXITRST_POLICY) Controls when the xHCI engine is brought out of reset due to a power ungate. |
1 | 0h | RW | USB2 Port Wake Unit Coupling Policy (USB2_PORT_WAKE_COUPLING_POLICY) Controls the trigger for USB2 Port Wake Units to initiate Port Level Power Off Preparation. |
0 | 0h | RW | USB3 Port Wake Unit Coupling Policy (USB3_PORT_WAKE_COUPLING_POLICY) Controls the trigger for USB3 Port Wake Units to initiate Port Level Power Off Preparation. |