Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Slave Status Register (SSTS) – Offset 10
All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll the register until a write takes effect before assuming that a write has completed internally.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
6:1 | - | - | Reserved
|
0 | 0b | RW/1C | HOST_NOTIFY_STS (HNS) The Intel PCH sets this bit to a 1 when it has completely received a successful Host Notify Command on the SMBus pins. Software reads this bit to determine that the source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this bit after reading any information needed from the Notify address and data registers by writing a 1 to this bit. Note that the Intel PCH will allow the Notify Address and Data registers to be over-written once this bit has been cleared. When this bit is 1, the Intel PCH will NACK the first byte (host address) of any new Host Notify commands on the SMBus. Writing a 0 to this bit has no effect. |