Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
SSP (GSPI) Status Register (SSSR) – Offset 8
The Enhanced SSP Status registers contain bits that signal overrun errors as well as the Transmit and Receive FIFO service requests. Each of these hardware-detected events signals an Interrupt request to the Interrupt controller. The Status register also contains flags that indicate when the Enhanced SSP is actively transmitting data, when the Transmit FIFO is not full, and when the Receive FIFO is not empty. One Interrupt signal is sent to the Interrupt Controller for each SSP. These events can cause an Interrupt: End-of-Chain, Receiver Time-out, Peripheral Trailing Byte, Receive FIFO overrun, Receive FIFO request, and Transmit FIFO request.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:22 | - | - | Reserved
|
21 | 0b | RW/1C | TUR (TUR) Transmit FIFO Under Run |
20 | - | - | Reserved
|
19 | 0b | RW/1C | TINT (TINT) Receiver Time-out Interrupt |
18 | 0b | RW/1C | PINT (PINT) Peripheral Trailing Byte Interrupt |
17:8 | - | - | Reserved
|
7 | 0b | RW/1C | ROR (ROR) Receive FIFO Overrun |
6 | 0b | RO | RFS (RFS) Receive FIFO Service Request |
5 | 0b | RO | TFS (TFS) Transmit FIFO Service Request |
4 | 0b | RO | BSY (BSY) SSP Busy |
3 | 0b | RO | RNE (RNE) Receive FIOF Not Empty |
2 | 1b | RO | TNF (TNF) Transmit FIFO Not Full |
1:0 | - | - | Reserved
|