Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Status and Command (BIOS_SPI_STS_CMD) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW/1C/V | Detected Parity Error (DPE) Detected Parity Error (DPE): |
30 | 0b | RW/1C/V | Signaled System Error (SSE) Signaled System Error (SSE): |
29 | 0b | RO | Received Master Abort (RMA) Hardwired to 0. |
28 | 0b | RO | Received Target Abort (RTA) Hardwired to 0. |
27 | 0b | RW/1C/V | Signaled Target Abort (STA)
|
26:25 | - | - | Reserved
|
24 | 0b | RO | Master Data Parity Error (MDPE) Hardwired to 0. |
23:22 | - | - | Reserved
|
21 | 0b | RO | 66 MHz Capable (MCAP) Not 66 MHz capable device. |
20 | 0b | RO | Capabilities List (CAPL) Hardwired to 0 indicating that a Capabilities List is not present. |
19 | 0b | RO | Interrupt Status (INTS) Hardwired to 0. |
18:11 | - | - | Reserved
|
10 | 1b | RO | Interrupt Disable (INTD) Hardwired to 1. INTx# interrupt is disabled. |
9 | 0b | RO | Fast Back to Back Enable (FBTBEN) Hardwired to 0. |
8 | 0b | RW | System Error Enable (SERREN) 0 = SERR# generation is disabled.1 = SERR# generation is enabled. |
7 | - | - | Reserved
|
6 | 0b | RW | Parity Error Response (PERRR) 0 = Disabled. The controller will not generate PERR# when a data parity error is detected.1 = Enabled. The controller will generate PERR# when a data parity error is detected. |
5 | - | - | Reserved
|
4 | 0b | RO | Memory Write and Invalidate Enable (MWRIEN) Hardwired to 0. |
3 | 0b | RO | Special Cycle Enable (SPCYC) Hardwired to 0. |
2 | 0b | RW | Bus Master Enable (BME) 0 = Disable1 = Enable |
1 | 0b | RW | Memory Space Enable (MSE) 0 = Disables memory mappedConfiguration space.1 = Enables memory mapped Configuration space. |
0 | 0b | RO | IO Space Enable (IOSE) Hardwired to 0. |