31:24 | 00h | RW | Throttle Period (TP) Throttle Period (TP): If any of the TNPT.DRXLTE or TNPT.DTXLTE bit is 1, this field defines the duration in milliseconds that defines the Throttling Window. When TNPT.TTG is set to 0, the effective Throttling Period is: 00h: 1 ms 01h: 2 ms : : FFh: 256 ms Note: The Throttle Period will have an uncertainty of +/-1 ms. When TNPT.TTG is set to 1, the effective Throttling Period is: 00h: 100 us 01h: 200 us : : FFh: 25.6 ms Note: The Throttle Period will have an uncertainty of +/-100 us. Note: To change the Link Throttling control bits, the DRXLTE and DTXLTE bits must be disabled first, change the value, and then re-enable the Link throttling. Note: If TNPT.TT is programmed to a value bigger than TNPT.TP, the hardware behavior is undefined. |
23:16 | 00h | RW | Throttle Time (TT) Throttle Time (TT): If any of the TNPT.DRXLTE or TNPT.DTXLTE bit is 1, this field defines the period of the Throttling Zone within the Throttling Window specified by TNPT.TP. The value specified in this field will be multiplied by the respective multiplier in TNPT.TSLxM fields depending on the throttling severity indication received together with the Throttling State change indication. When TNPT.TTG is set to 0, the effective Throttle Time is: 00h: 1 ms 01h: 2 ms : 3Fh: 64 ms Others: Alias to 3Fh. Note: The Throttle Period will have an uncertainty of +/-1 ms. When TNPT.TTG is set to 1, the effective Throttle Time is: 00h: 100 us 01h: 200 us : 3Fh: 6.4 ms Note: The Throttle Period will have an uncertainty of +/-100 us. Note: If the reserved encoding is programmed to this field, hardware will behave the same as if the field is programmed to 3Fh. Note: Since the design is using a 1 ms tick for this timer, the Throttle Time will have an uncertainty of +/-1 ms. Note: To change the Link Throttling control bits, the DRXLTE and DTXLTE bits must be disabled first, change the value, and then re-enable the Link throttling. Note: If TNPT.TT is programmed to a value bigger than TNPT.TP, the hardware behavior is undefined. |
15:12 | - | - | Reserved |
11:10 | 10b | RW | Throttling Severity Level 3 Multiplier (TSL3M) Throttling Severity Level 3 Multiplier (TSL3M): This register determines the multiplier to be used together with the TNPT.TT field to specify the period of the Throttling Zone within the Throttling Window. 00b: x1 01b: x2 10b: x4 11b: Always throttling. Note: To change the Link Throttling control bits, the DRXLTE and DTXLTE bits must be disabled first, change the value, and then re-enable the Link throttling. |
9:8 | 01b | RW | Throttling Severity Level 2 Multiplier (TSL2M) Throttling Severity Level 2 Multiplier (TSL2M): This register determines the multiplier to be used together with the TNPT.TT field to specify the period of the Throttling Zone within the Throttling Window. 00b: x1 01b: x2 10b: x4 11b: Always throttling. Note: To change the Link Throttling control bits, the DRXLTE and DTXLTE bits must be disabled first, change the value, and then re-enable the Link throttling. |
7:6 | 00b | RW | Throttling Severity Level 1 Multiplier (TSL1M) Throttling Severity Level 1 Multiplier (TSL1M): This register determines the multiplier to be used together with the TNPT.TT field to specify the period of the Throttling Zone within the Throttling Window. 00b: x1 01b: x2 10b: x4 11b: No throttling. Note: To change the Link Throttling control bits, the DRXLTE and DTXLTE bits must be disabled first, change the value, and then re-enable the link throttling |
5:4 | 11b | RW | Throttling Severity Level 0 Multiplier (TSL0M) Throttling Severity Level 0 Multiplier (TSL0M): This register determines the multiplier to be used together with the TNPT.TT field to specify the period of the Throttling Zone within the Throttling Window. 00b: x1 01b: x2 10b: x4 11b: No throttling. Note: To change the Link Throttling control bits, the DRXLTE and DTXLTE bits must be disabled first, change the value, and then re-enable the Link throttling. |
3:2 | - | - | Reserved |
1 | 0b | RW | Dynamic RX Link Throttling Enable (DRXLTE) Dynamic RX Link Throttling Enable (DRXLTE): 0b: Dynamic Link RX Throttling mechanism is disabled. 1b: Dynamic Link RX Throttling mechanism is enabled. PCIe Root Port will induce the link to enter RXL0s. The duty cycle of the throttling window is configurable based on the throttling severity. Note: This field can only be set if the remote component supports TXL0s. |
0 | 0b | RW | Dynamic TX Link Throttling Enable (DTXLTE) Dynamic TX Link Throttling Enable (DTXLTE): 0b: Dynamic Link TX Throttling mechanism is disabled. 1b: Dynamic Link TX Throttling mechanism is enabled. PCIe Root Port will induce the link to enter TXL0s. The duty cycle of the throttling window is configurable based on the throttling severity. Note: This field can only be set if the remote component supports TXL0s. |