Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Uncorrectable Error Status (UES) – Offset 104
This register must maintain its state through a platform reset. It loses its state upon loss of core power.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:22 | - | - | Reserved
|
21 | 0b | RW/1C/V/P | ACS Violation Status (AVS) Indicates an ACS Violation is logged |
20 | 0b | RW/1C/V/P | Unsupported Request Error Status (URE) Indicates an unsupported request was received. |
19 | 0b | RO | ECRC Error Status (EE) ECRC is not supported. |
18 | 0b | RW/1C/V/P | Malformed TLP Status (MT) Indicates a malformed TLP was received. |
17 | 0b | RW/1C/V/P | Receiver Overflow Status (RO) Indicates a receiver overflow occurred. |
16 | 0b | RW/1C/V/P | Unexpected Completion Status (UC) Indicates an unexpected completion was received. |
15 | 0b | RW/1C/V/P | Completor Abort Status (CA) Indicates a completer abort was received |
14 | 0b | RW/1C/V/P | Completion Timeout Status (CT) Indicates a completion timed out. This is signaled if Completion Timeout is enabled and a completion fails to return within the amount of time specified by the Completion Timeout Value |
13 | 0b | RO | Flow Control Protocol Error Status (FCPE) Not supported. |
12 | 0b | RW/1C/V/P | Poisoned TLP Status (PT) Indicates a poisoned TLP was received. |
11:6 | - | - | Reserved
|
5 | 0b | RO | Surprise Down Error Status (SDE) Surprise Down is not supported. |
4 | 0b | RW/1C/V/P | Data Link Protocol Error Status (DLPE) Indicates a data link protocol error occurred. |
3:1 | - | - | Reserved
|
0 | 0b | RO | Training Error Status (TE) Not supported. |