Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
USB Status (USBSTS) – Offset 84
This register indicates pending interrupts and various states of the Host controller. The status resulting from a transaction on the serial bus is not indicated in this register. See the Interrupts description in section 4 of the xHCI specification for additional information concerning interrupt conditions.
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has no effect.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:13 | - | - | Reserved
|
12 | 0b | RO | Host Controller Error (HCE) This flag shall be set to indicate that an internal error condition has been detected which requires software to reset and re-initialize the xHC. |
11 | 0b | RO | Controller Not Ready (CNR) 0 = Ready |
10 | 0b | RW/1C | Save/Restore Error (SRE) If an error occurs during a Save or Restore operation this bit shall be set to 1b. This bit shall be cleared to 0b when a Save or Restore operation is initiated or when written with 1b. |
9 | 0b | RO | Restore State Status (RSS) When the Controller Restore State (CRS) flag in the USB_CMDregister is written with 1b this bit shall be set to 1b and remain set while the xHC restores its internalstate. |
8 | 0b | RO | Save State Status (SSS)
|
7:5 | - | - | Reserved
|
4 | 0b | RW/1C | Port Change Detect (PCD) This bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the xHC, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, overcurrent change, enable/ disable change and connect status change). Regardless of the implementation, when this bit is readable (that is, in the D0 state), it must provide a valid view of the Port Status registers. |
3 | 0b | RW/1C | Event Interrupt (EINT) The xHC sets this bit to 1b when the Interrupt Pending (IP) bit of any Interrupter is transitions from 0b to 1b. Software that uses EINT shall clear it prior to clearing any IP flags. A race condition will occur if software clears the IP flags then clears the EINT flag, and between the operations another IP ‘0’ to '1' transition occurs. In this case the new IP transition will be lost. |
2 | 0b | RW/1C | Host System Error (HSE) The xHC sets this bit to 1b when a serious error is detected, either internal to the xHC or during a host system access involving the xHC module. Conditions that set this bit to ‘1’ include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the xHC clears the Run/Stop (R/S) bit in the USB_CMD register to prevent further execution of the scheduled TDs. If the HSEE bit in the USB_CMD register is 1b, the xHC shall also assert out-ofband error signaling to the host. |
1 | - | - | Reserved
|
0 | 1b | RO | HCHalted (HCH) This bit is a ‘0’ whenever the Run/Stop (R/S) bit is set to 1b. The xHC sets this bit to 1b after it has stopped executing as a result of the Run/Stop (R/S) bit being cleared to 0b, either by software or by the xHC hardware (for example, internal error). If this bit is set to1b, then SOFs, microSOFs, or Isochronous Timestamp Packets (ITP) shall not be generated by the xHC. |