4th Gen Intel® Xeon® Processor Scalable Family

Specification Update

ID 772415
Date 06/14/2024
Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Preface Identification Information Component Marking Information Summary Tables of Changes Errata Details Specification Changes Specification Clarifications Documentation Changes
Legal Disclaimer
Revision History
Preface
Preface Related Documents Nomenclature
Related Documents
Nomenclature
Identification Information
Component Identification via Programming Interface
Component Identification via Programming Interface
Component Marking Information
Summary Tables of Changes
Summary Tables of Changes Codes Used in Summary Tables Errata Summary Table
Codes Used in Summary Tables
Errata Summary Table
Errata Details
Specification Changes
Specification Clarifications
Documentation Changes
Legal Disclaimer
Revision History
Preface
Identification Information
Component Marking Information
Summary Tables of Changes
Errata Details
Specification Changes
Specification Clarifications
Documentation Changes

Component Identification via Programming Interface

The 4th Gen Intel® Xeon® Scalable Processors stepping can be identified by the following register contents:

CPUID (Offset:1Ah-19h) Extended Family ID1 Extended Model2 Reserved Processor Type3 Processor Family4 Processor Model5 Processor Stepping6
Bit 27:20 19:16 15:14 13:12 11:8 7:4 3:0
XCC E-5/E-4,

MCC S-3/S-2,

HBM B-3

00000000b 1000b 0b 0110b 1111b 1111b

Notes:
  1. The Extended Family, bits [27:20] are used in conjunction with the Processor Family, specified in bits [11:8], to indicate whether the processor belongs to the Intel® 386™, Intel® 486™, Pentium®, Pentium® Pro, Pentium® 4, Intel® Core™ processor families, Intel® Core™ ix families, and Intel® Xeon® processor families.
  2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processor’s family.
  3. The Processor Type, specified in bit [12] indicates whether the processor is an original OEM processor, an Intel® OverDrive processor, or a dual processor (capable of being used in a dual processor system).
  4. The Processor Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
  5. The Processor Model, bits [7:4] corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.
  6. The Processor Stepping, bits [3:0] indicates the revision number of that model. See Table: Component Identification via Capability Registers for the processor stepping ID number in the CPUID information.

To find the mapping between a processor's CPUID and its Family/Model number, see the Intel® 64 and IA-32 Architectures Software Developer Manual Combined Volumes.

A complete description of the processor identification and feature determination is located in Chapter 20.

When EAX is set to a value of ‘1,’ the CPUID instruction returns the Processor Family, Extended Model ID, Processor Type, Family, Model, and Stepping together referred as the processor signature value, in the EAX register. Note that after reset, the EDX processor will report the processor signature value in both the EDX and the EAX registers.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX, and EDX general purpose registers after the CPUID instruction is executed with a 2 in the EAX register. Special uses of general purpose registers include: EAX (Accumulator for operands and results data), EBX (Pointer to data in the DS segment), ECX (Counter for string and loop operations), and EDX (I/O pointer).

The 4th Gen Intel® Xeon® Scalable Processors Stepping can also be identified in 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids Registers Specification

Component Identification via Capability Registers

Physical Chip Stepping SEGMENT, WAYNESS CPUID SEGMENT1 [Bits 5:3] WAYNESS2 [Bits 1:0] PHYSICAL_​CHOP3 [Bits 7:6]
Offset [B:31, D:30, F:3] + 84h Offset [B:31, D:30, F:3] + 94h
5 4 3 1 0 7 6
XCC E-5/E-4 Server, 1S 806F8/806F7 1 1 1 0 0 1 1
XCC E-5/E-4 Server, 2S 806F8/806F7 1 1 1 0 1 1 1
XCC E-5/E-4 Server, 4S 806F8/806F7 1 1 1 1 0 1 1
XCC E-5/E-4 Server, 8S 806F8/806F7 1 1 1 1 1 1 1
MCC S-3/S-2 Server, 1S 806F8/806F7 1 1 1 0 0 0 1
MCC S-3/S-2 Server, 2S 806F8/806F7 1 1 1 0 1 0 1
MCC S-3/S-2 Server, 4S 806F8/806F7 1 1 1 1 0 0 1
HBM B-3 Server, 1S 806F8 1 1 1 0 0 1 1
HBM B-3 Server, 2S 806F8 1 1 1 0 1 1 1
HBM B-3 Server, 4S 806F8 1 1 1 1 0 1 1

Notes:

  1. The SEGMENT, bits [5:3] corresponds to 111: Server; 011: Server-FPGA; 001: Server-Fabric; 100: HPC; 110: Server-Atom; 010: Workstation; 000: HEDT; Others: Reserved.
  2. The WAYNESS, bits [1:0] corresponds to 00=1S, 01=2S, 10 = 4S, 11 = 8S.
  3. The PHYSICAL_​CHOP, bits [7:6] corresponds to 11:XCC; 01:MCC; 11:HBM.

The 4th Gen Intel® Xeon® Scalable Processors Capability Registers can also be identified in 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids Registers Specification .

Component Marking Information