| SPR1 | No Fix | No Fix | No Fix | IPSR May Not Function Correctly |
| SPR2 | No Fix | No Fix | No Fix | Poison Data Reported Instead of a CS Limit Violation |
| SPR3 | No Fix | No Fix | No Fix | Monitor Instructions to Legacy VGA Region May Fail |
| SPR4 | No Fix | No Fix | No Fix | TILEDATA State May Be Saved Incorrectly |
| SPR5 | No Fix | No Fix | No Fix | A Poison Data Event May Not be Serviced if a Data Breakpoint Occurs on an AMX Tile-Load or AVX Gather or REP MOVS Instruction |
| SPR6 | No Fix | No Fix | No Fix | IFS MSRs Will Ignore a Non-Zero EDX Value And Not Signal a #GP |
| SPR7 | No Fix | No Fix | No Fix | Processor May Signal Spurious #GP Fault |
| SPR8 | No Fix | No Fix | No Fix | A Break Point May be Hit Twice When a VM Exit Without Commit Occurs |
| SPR9 | No Fix | No Fix | No Fix | Faulted XRSTORS Instruction May Result in Unexpected X87 FTW Value |
| SPR10 | No Fix | No Fix | No Fix | Error Conditions Detected During Cold Reset May Not be Cleared by Subsequent Warm Reset |
| SPR11 | No Fix | No Fix | No Fix | DSA/IAX Does Not Log The E2E Prefix Bit And The Prefix-Type Bits in AERTLPPLOG1 |
| SPR12 | No Fix | No Fix | No Fix | The Processor May Drop Noncompliant Posted Peer-to-peer Transactions |
| SPR13 | No Fix | No Fix | No Fix | Certain Bits in IA32_MC5_STATUS Register Will Always Return 0 |
| SPR14 | No Fix | No Fix | No Fix | Occupancy Interrupt Handle is Not Checked Against Interrupt Table Size |
| SPR15 | No Fix | No Fix | No Fix | Processor May Incorrectly Set PFD Assisted in Correction Bit in Memory Controller |
| SPR16 | No Fix | No Fix | No Fix | DSA CMDSTATUS Register May Not Reflect Correct Hardware Status |
| SPR17 | No Fix | No Fix | No Fix | Remapping Hardware May Set Access/Dirty Bits in a First-stage Page-table Entry |
| SPR18 | No Fix | No Fix | No Fix | System Software May Not Receive VT-d Fault SPT.3 For Non-Zero Writes to b[191:HAW+128] |
| SPR19 | No Fix | No Fix | No Fix | APCTL.APNGE Should be RW Instead of RWS |
| SPR20 | No Fix | No Fix | No Fix | CXL Device May Not Receive Viral |
| SPR21 | No Fix | No Fix | No Fix | OOBMSM TSC Will be 320ns Behind The Globally Aligned Counter |
| SPR22 | No Fix | No Fix | No Fix | Performance Monitoring Event Coherent_ops May Undercount |
| SPR23 | No Fix | No Fix | No Fix | PCIe Link Re-Equalization May Not Occur if Link is in L1 State |
| SPR24 | No Fix | No Fix | No Fix | Machine Check Bank 4 UCNA Errors May Not be Signaled |
| SPR25 | No Fix | No Fix | No Fix | DSA/IAA Use of Priv and PASID |
| SPR26 | No Fix | No Fix | No Fix | Reserved(0) Check For a PASID Table Entry May Not Happen For a DMA Request |
| SPR27 | No Fix | No Fix | No Fix | Remapping Hardware May Not Generate a Page Request Group Response Message While Operating in Legacy Mode or Abort DMA Mode |
| SPR28 | No Fix | No Fix | No Fix | Remapping Hardware May Abort ZLR to Second-Stage Write Only Pages |
| SPR29 | No Fix | No Fix | No Fix | Remapping Hardware with Major Version Number 6 Incorrectly Advertises the ESRTPS Support |
| SPR30 | No Fix | No Fix | No Fix | Platform May Hang if System Software Sends a Page Group Response or DevTLB Invalidation to Non-existent Requester ID |
| SPR31 | No Fix | No Fix | No Fix | Remapping Hardware Does Not Perform Reserved (0) Check in Page Response Descriptor |
| SPR32 | No Fix | No Fix | No Fix | Remapping Hardware Implements b[31:16] of the three Event Data Registers (VTDBAR offsets 0x3C, 0xA4, and 0xE4) as Read-Writable |
| SPR33 | No Fix | No Fix | No Fix | IAA Do Not Report Overlap Errors For AECS Size of 2GB or Greater |
| SPR34 | No Fix | No Fix | No Fix | DSA/IAA Invalid TC Not Reported in The SWERROR Register |
| SPR35 | No Fix | No Fix | No Fix | IAA Unaligned Completion Record Address Error is Not Reported in SWERROR Register |
| SPR36 | No Fix | No Fix | No Fix | Intel® UPI Link Not Resetting When L1 Mismatch Occurs Between Local and Remote Sockets |
| SPR37 | No Fix | No Fix | No Fix | DSA/IAA May Fail to Log an MDPE Error For Back-to-Back Parity Errors |
| SPR38 | No Fix | No Fix | No Fix | Relaxed Ordering Not Disabled by DEVCTL.ERO bit for DSA/IAA Upstream Transactions |
| SPR39 | No Fix | No Fix | No Fix | System Address Logged For WDB Parity Errors May be Incorrect |
| SPR40 | No Fix | No Fix | No Fix | Incorrect MCACOD For L2 MCE |
| SPR41 | No Fix | No Fix | No Fix | System May Hang Due to Full LLRB |
| SPR42 | No Fix | No Fix | No Fix | IAA May Fail to Properly Decode Data With a Large Header |
| SPR43 | No Fix | No Fix | No Fix | Memory Controller Violates JEDEC RCD tCSALT Timing |
| SPR44 | Fixed | Fixed | Fixed | Wrong CKE Signal Used on 1 DPC 3DS 4H Configs |
| SPR45 | No Fix | No Fix | No Fix | Address May Not be Logged For a UCR Error Detected in The MLC |
| SPR46 | No Fix | No Fix | No Fix | VT-d DMA Remapping Hardware May Hang if it Encounters Page Request Queue Overflow Condition |
| SPR47 | No Fix | No Fix | No Fix | Receiver Common Mode Input Impedance May be Below Specification When Interface is Powered Down |
| SPR48 | No Fix | No Fix | No Fix | Remapping Hardware Will Not Report The PASID Value For RTA.2 Faults in Modes Other Than Scalable Mode |
| SPR49 | No Fix | No Fix | No Fix | Remapping Hardware Does Not Perform a Reserved(0) Check in Interrupt Remap Table Entry |
| SPR50 | No Fix | No Fix | No Fix | Processor PCIe Root Port Link Spurious Data Parity Error May be Reported |
| SPR51 | No Fix | No Fix | No Fix | Mismatch Between UboxErrMisc and MCI_STATUS Registers Error Logs |
| SPR52 | No Fix | No Fix | No Fix | CHA UCNA Errors May be Incorrectly Controlled by MCi_CTL Enable Bits |
| SPR53 | No Fix | No Fix | No Fix | Reading The PPERF MSR May Not Return Correct Values |
| SPR54 | No Fix | No Fix | No Fix | No #GP Will be Signaled When Setting MSR_MISC_PWR_MGMT.ENABLE_SDC if MSR_MISC_PWR_MGMT.LOCK is Set |
| SPR55 | No Fix | No Fix | No Fix | System May Experience an Internal Timeout Error When an Internal Parity Error Occurs While Working With Intel® AMX |
| SPR56 | No Fix | No Fix | No Fix | Last Branch Records May Not Survive Warm Reset |
| SPR57 | No Fix | No Fix | No Fix | Single Step on Branches Might be Missed When VMM Enables Notification On VM Exit |
| SPR58 | No Fix | No Fix | No Fix | Incorrect #CP Error Code on UIRET |
| SPR59 | No Fix | No Fix | No Fix | #GP May be Serviced Before an Instruction Breakpoint |
| SPR60 | No Fix | No Fix | No Fix | Unexpected #PF Exception Might Be Serviced Before a #GP Exception |
| SPR61 | No Fix | No Fix | No Fix | VMX-Preemption Timer May Not Work if Configured With a Value of 1 |
| SPR62 | No Fix | No Fix | No Fix | User Interrupt Might be Delayed |
| SPR63 | No Fix | No Fix | No Fix | VM Exit Qualification May Not be Correctly Set on APIC Access While Serving a User Interrupt |
| SPR64 | No Fix | No Fix | No Fix | Software Tuning That Relies on PCLS Values May Experience Inaccurate Event Counts |
| SPR65 | No Fix | No Fix | No Fix | Multiple SGX_Doorbell_Errors on Ubox Response Mismatch |
| SPR66 | Fixed | Fixed | Fixed | ECS Readout Fails on Mixed Mode Systems |
| SPR67 | No Fix | No Fix | No Fix | Intel DSA/IAA Completion Record is Not Written For Non-Completion Record Invalid Traffic Classes |
| SPR68 | No Fix | No Fix | No Fix | Intel IAA Expand Operation With PRLE Format Input May Return an Error |
| SPR69 | No Fix | No Fix | No Fix | Intel IAA Compression with Compress Bit Order Set May Produce an Odd Number of Bytes |
| SPR70 | No Fix | No Fix | No Fix | Intel IAA Source 2 Not Written Properly When Source 2 Size is 32 Bytes |
| SPR71 | No Fix | No Fix | No Fix | Intel IAA May Not Report Invalid Filter Flags Status Code When Source 2 Bit Order Field is Set |
| SPR72 | No Fix | No Fix | No Fix | Intel IAA Does Not Allow Source 1 Size to be 0 For Expand Operation |
| SPR73 | No Fix | No Fix | No Fix | Intel® DSA/IAA And WQ Configuration Registers May be Incorrectly Updated |
| SPR74 | No Fix | No Fix | No Fix | Invalid Flags Field of The Completion Record May Not be Set Correctly For Intel IAA Compression Operation |
| SPR75 | No Fix | No Fix | No Fix | With Intel® SGX Disabled, Software That Relies on ENCLVexiting May Not Function as Expected |
| SPR76 | No Fix | No Fix | No Fix | Headers Logged in AERHDRLOG for an AER Error for Intel DSA/IAA may be Incorrect |
| SPR77 | No Fix | No Fix | No Fix | Intel DSA/IAA May Fail to Send an ERR_FATAL Message if a Non-Fatal Error Occurs in The Same Cycle |
| SPR78 | No Fix | No Fix | No Fix | Intel DSA/IAA May Fail to Log an Unexpected Completion Error For an Invalid ATS Response |
| SPR79 | No Fix | No Fix | No Fix | Intel IAA Compression Output Buffer Overflow Error May be Incorrectly Reported |
| SPR80 | No Fix | No Fix | No Fix | Intel® QuickAssist Technology Accelerator May Violate ATS Invalidation Completion Ordering |
| SPR81 | No Fix | No Fix | No Fix | Intel® QuickAssist Technology Accelerator Device May Not Invalidate PASID SupervisorPrivilege Translations Privilege Translations |
| SPR82 | Fixed | Fixed | Fixed | The Time-Stamp Counter May Report an Incorrect Value |
| SPR83 | No Fix | No Fix | No Fix | UPI Machine Check Bank May Not Report The Most Recently Logged Error |
| SPR84 | No Fix | No Fix | No Fix | PECI Wire Host may Continuously Receive a Completion Code of 0x80 |
| SPR85 | No Fix | No Fix | No Fix | DDR5 9x4 DIMMs ECS Data May be Reported Incorrectly |
| SPR86 | No Fix | No Fix | No Fix | RETRY_RD_ERR_LOG_MISC.DDR5_9x4_half_device Bit Maybe Incorrect |
| SPR87 | No Fix | No Fix | No Fix | PIROM Reports The Wrong 2 DPC Speed For Processors With Less Than 4800 MT/s 1 DPC Speed |
| SPR88 | No Fix | No Fix | No Fix | An MDF Parity Error May Incorrect Set The Overflow Bit |
| SPR89 | No Fix | No Fix | No Fix | Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be Observed |
| SPR90 | No Fix | No Fix | No Fix | CPUID Reports Incorrect Number of Ways For The Load DTLB |
| SPR91 | No Fix | No Fix | No Fix | Intel PT Trace May Contain Incorrect Data When Configured With Single Range Output Larger Than 4KB |
| SPR92 | No Fix | No Fix | No Fix | On Instructions Longer Than 15 Bytes, #GP Exception is Prioritized And Delivered Over #CP Exception |
| SPR93 | No Fix | No Fix | No Fix | Mismatch on DR6 Value When Breakpoint Match is on Bitmap Address |
| SPR94 | No Fix | No Fix | No Fix | RTM Abort Status May be Incorrect For INT1/INT3 Instructions |
| SPR95 | No Fix | No Fix | No Fix | WRMSR to Reserved Bits of IA32_L3_QOS_Mask_15 Will Not signal a #GP |
| SPR96 | No Fix | No Fix | No Fix | x87 FDP Value May be Saved Incorrectly |
| SPR97 | No Fix | No Fix | No Fix | Debug Exceptions May Be Lost or Misreported When MOV SS or POP SS Instruction is Not Followed By a Write to SP |
| SPR98 | No Fix | No Fix | No Fix | Exit Qualification For EPT Violations on Instruction Fetches May Incorrectly Indicate That The Guest-physical Address Was Writeable |
| SPR99 | No Fix | No Fix | No Fix | Processor May Generate Spurious Page Faults On Shadow Stack Pages |
| SPR100 | No Fix | No Fix | No Fix | Processor May Hang if Warm Reset Triggers During BIOS Initialization |
| SPR101 | No Fix | No Fix | No Fix | IA32_MC1_STATUS MSR May Not Log Errors When IA32_MC1_CTL MSR is Set to Not Signal Errors |
| SPR102 | No Fix | No Fix | No Fix | System May Hang When Bus-Lock Detection Is Enabled And EPT Resides in Uncacheable Memory |
| SPR103 | No Fix | No Fix | No Fix | OFFCORE_REQUESTS_OUTSTANDING Performance Monitoring Events May be Inaccurate |
| SPR104 | No Fix | No Fix | No Fix | Incorrect MCACOD For L2 Prefetch MCE |
| SPR105 | No Fix | No Fix | No Fix | Call Instruction Wrapping Around The 32-bit Address Boundary May Return to Incorrect Address |
| SPR106 | No Fix | No Fix | No Fix | ADDDC Reverse Sparing May Lead to Incorrect Data |
| SPR107 | No Fix | No Fix | No Fix | SGX ENCLU[EACCEPT] Will Not Cause #GP When TCS.PREVSPP is Non-zero |
| SPR108 | No Fix | No Fix | No Fix | Setting MISC_FEATURE_CONTROL.DISABLE_THREE_STRIKE_CNT Does Not Prevent The Three-strike Counter From Incrementing |
| SPR109 | No Fix | No Fix | No Fix | Mismatch Between UboxErrMisc and MCI_STATUS Registers Error Logs |
| SPR110 | No Fix | No Fix | No Fix | SST-TF May Fail to Report an Error if Turbo is Disabled |
| SPR111 | No Fix | No Fix | No Fix | Unexpected Rollover in MBM Counters |
| SPR112 | Fixed | Fixed | Fixed | In 96bit ECC Mode, a Correctable Error May be Incorrectly Logged in RETRY_RD_ERR_LOG With UC Bit Set |
| SPR113 | No Fix | No Fix | No Fix | System Crash Observed on Host When TD Private Pages Are Not Zeroed Out if Reused For Non-TD SW |
| SPR114 | No Fix | No Fix | No Fix | IA32_MC2_ADDR And IA32_MC2_MISC MSRs Will be Cleared on Warm Reset |
| SPR115 | No Fix | No Fix | No Fix | Multiple Write CRC Errors May Lead to System Hang |
| SPR116 | No Fix | No Fix | No Fix | Intel DSA/IAA CTO Errors May Inconsistently Update the Prefix Log and Prefix Log Present Flag |
| SPR117 | No Fix | No Fix | No Fix | RTIT_CTL.TRACE_EN May be Disabled at BIOS_DONE Even if it Was Previously Enabled |
| SPR118 | No Fix | No Fix | No Fix | WRMSR to a Few Core MSRs Might be Overwritten |
| SPR 119 | Fixed | Fixed | Fixed | Virtualize IA32_SPEC_CTRL VM-execution Control Does Not Properly Virtualize Bits [63:32] of IA32_SPEC_CTRL |
| SPR 120 | No Fix | No Fix | No Fix | SPR120. Performance Monitoring Events used by TMA May be Inaccurate |
| SPR 121 | No Fix | No Fix | No Fix | SPR121. Performance Monitoring Event IDQ.MS_UOPS May Undercount |
| SPR 122 | Fixed | Fixed | Fixed | SPR122. CHA TOR Timeout May Occur |
| SPR 123 | No Fix | No Fix | No Fix | SPR123. ECS Reads May Fail to Complete in Certain Memory Configurations and Conditions |
| SPR 124 | Fixed | Fixed | Fixed | SPR124. A Write to The TSC_Deadline MSR May Cause an Unexpected Timer Interrupt |
| SPR125 | No Fix | No Fix | No Fix | Processor Performance Monitor Discovery Table Incorrectly Reports Data for Intel® UPI Port 3 on MCC SKUs |
| SPR126 | No Fix | No Fix | No Fix | Certain PCIe Devices Are Not Accessible Out-of-Band With Local Bus Number |
| SPR127 | No Fix | No Fix | No Fix | Remapping Hardware May Encounter Incorrect Error Code in Invalidation Queue Error Record Register |
| SPR128 | No Fix | No Fix | No Fix | Disabling The APIC While an Interrupt is Being Delivered May Cause a System Hang |