Component Identification via Programming Interface

Intel® Xeon® 6700-Series Processor with E-Cores

Specification Update

ID	Date	Version	Classification
820922	12/10/2025		Public

The Intel® Xeon® 6700-Series Processor with E-Cores stepping can be identified by the following register contents.

Intel® Xeon® 6700-Series Processor with E-Cores Identification

CPUID	Extended Family¹	Extended Model²	Reserved	Processor Type³	Processor Family⁴	Processor Model⁵	Processor Stepping⁶
Bit	27:20	19:16	15:14	13:12	11:8	7:4	3:0
HDCC	0h	Ah	0h	0h	6h	Fh	3h

Notes:

The Extended Family, bits [27:20], is used in conjunction with the Family Code, specified as bits [11:8], to indicate whether the processor belongs to the Intel386™, Intel486™, Pentium®, Pentium® Pro, Pentium® 4, Intel® Core™ processor family, or the Intel® Core™ i7 family.

The Extended Model ID, bits [7:0] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processor’s family.

The Processor Type, specified in bit [12] indicates whether the processor is an original OEM processor, an Intel® OverDrive processor, or a dual processor (capable of being used in a dual processor system).

The Processor Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.

The Processor Model, bits [7:4] corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

The Processor Stepping, bits [3:0] indicates the revision number of that model. See Table: Component Identification via Capability Registers for the processor stepping ID number in the CPUID information.

This location contains the CPUID, Processor Type, Family, Model, and Stepping. The CPUID field is a copy of the results in EAX[15:0] from Function 1 of the CPUID instruction. Writes to this register have no effect. Data format is hexadecimal.

To find the mapping between a processor's CPUID and its Family/Model number, see the Intel® 64 and IA-32 Architectures Software Developer Manual Combined Volumes.

A complete description of the processor identification and feature determination is located in Chapter 20.

When EAX is set to a value of ‘1,’ the CPUID instruction returns the Processor Family, Extended Model ID, Processor Type, Family, Model, and Stepping together referred as the processor signature value, in the EAX register. Note that after reset, the EDX processor will report the processor signature value in both the EDX and the EAX registers.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX, and EDX general purpose registers after the CPUID instruction is executed with a 2 in the EAX register. Special uses of general purpose registers include: Accumulator for operands and results data (EAX), Pointer to data in the DS segment (EBX),Counter for string and loop operations (ECX), and I/O pointer (EDX).

Component Identification via Capability Registers

Physical Chip	Stepping	SEGMENT, WAYNESS	CPUID	SEGMENT¹ [Bits 5:3]			WAYNESS² [Bits 1:0]
				Offset [B:31, D:30, F:3] + 84h
				5	4	3	1	0
HDCC	C	Server, 1S	0xA06F3	1	1	1	0	0
HDCC	C	Server, 2S	0xA06F3	1	1	1	0	1

Notes:

Bits[5:3] SEGMENT:
- 111: Server SP
- 110: RSVD
- 101: Server AP
- 100: RSVD
- 011: Server DE
- 010: Server Atom
- 001: Workstation
- 000: HEDT
  Also, refer to CAPID5_[12:9]4 bits Sub-segment SKU for definitions.
Bits[12:9] SUB_SEGMENT:
- 0000 = Mainstream
- 0001 = Rich 1S
- 0010 = Edge
- 0100 = Value
  All other values are reserved.

Bits[1:0] WAYNESS (max wayness):
- 00 = 1S
- 01 = 2S
- 10 = 4S
- 11 = 8S