Direct Enhanced Serial Peripheral Interface (Direct eSPI)

Legal Disclaimer
Revision History
Introduction
PCH Controller Device IDs
- Revision IDs
- Device IDs
Memory Mapping
- Functional Description
- Memory Map
Audio Voice and Speech
Ballout Definition
Connectivity Integrated (CNVi)
Controller Link
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Direct Media Interface (DMI)
Enhanced Serial Peripheral Interface (eSPI)
Gigabit Ethernet Controller
Host System Management Bus (SMBus) Controller
Integrated Sensor Hub (ISH)
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers
PCI Express* (PCIe*)
Real Time Clock (RTC)
- Signal Description
- I/O Signal Planes and States
Serial ATA (SATA)
Serial Peripheral Interface (SPI)
System Clocks
- Integrated Clock Controller (ICC)
  - Signal Descriptions
- I/O Signal Pin States
System Management Interface and SMLink
Touch Host Controller (THC)
Universal Serial Bus (USB)
General Purpose Input and Output
- Functional Description
- Signal Description
GPIO Serial Expander
Private Configuration Space Port ID
Security Firmware Engines
- Intel® Converged Security and Management Engine (Intel® CSME)
- Intel® Silicon Security Engine
System Management
- Theory of Operation
  - TCO Modes
Testability and Monitoring
- Signal Description
- I/O Signal Planes and States
Miscellaneous Signals
Processor Sideband Signals
- Signal Description
- I/O Signal Planes and States
Power Delivery
- Power and Ground Signals
Power Management
Thermal Sensor
Electrical Characteristics

The Direct eSPI interface is used in order to support the secure eSPI link between the processor and the PCH. The processor is a Direct eSPI controller and PCH is a Direct eSPI target. The Direct eSPI interface features as below.

1.8 V support only.

Compliant to eSPI base specification 1.0.

Supports 50 MHz Single/Dual/Quad modes.

The Direct eSPI interface have a return clock eSPI_RCLK. In order to improve the eSPI bandwidth between the processor and the PCH, an eSPI return clock is used to increase the eSPI clock frequency from 50 MHz to 100 MHz. The PCH loopbacks the eSPI clock and returns the eSPI_RCLK to the processor. The PCH launches the eSPI response on the new return clock eSPI_RCLK.

Acronyms

Acronyms	Description
OOB	Out-of-Band
TAR	Turn-around cycle
Intel^® CSE	Intel^® Converged Security Engine
VW	Virtual Wire

References

Specification	Document Number/Location
Enhanced Serial Peripheral Interface (eSPI) Specifications	https://downloadcenter.intel.com/download/27055/eSPI

Functional Description

Signal Description Functional Description