Intel® 800 Series Chipset Family Platform Controller Hub (PCH)
Datasheet, Volume 1 of 2
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| PCH JTAG Signals | ||
| PCH_JTAG_TCK | I/O | Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. |
| PCH_JTAG_TMS | IOD | Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. |
| PCH_JTAG_TDI | IOD | Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI. |
| PCH_JTAG_TDO | IOD | Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. |
| PCH_JTAG_TRST# | I/O | Test Reset(TRST): Resets the Test Access Port (TAP) logic. This signal should be driven low during power-on Reset. |
| JTAGX | I/O | This pin is used to support merged debug port topologies. |
| DBG_PMODE | O | ITP Power Mode Indicator. This signal is used to transmit |
| PRDY# | IOD | Probe Mode Ready: PRDY# is a processor output used by debug tools to determine processor debug readiness. |
| PREQ# | IOD | Probe Mode Request: PREQ# is used by debug tools to request debug operation of the processor. |
| TRIGGER_IN | I | This pin is used for debug support. |
| TRIGGER_OUT | O | This pin is used for debug support. |
| GPP_J11/DAM | O | Debug Authentication Mode. |
| Boundary Scan Sideband Signals and Debug for I3C | ||
| GPP_J10/BPKI3C_SCL/BSSB_LS_TX | I/O | BPKI3C_SCL:Debug for I3C Clock BSSB_LS_TX: Boundary Scan Sideband Low Speed Transmit for debug purposes |
| GPP_J09/BPKI3C_SDA/BSSB_LS_RX | I/O | BPKI3C_SDA:Debug for I3C Data BSSB_LS_RX:Boundary Scan Sideband Low Speed Receive for debug purposes |
| Boot Halt Signal and Fuse Break | ||
| GPP_J07/BOOTHALT# | IOD | Boot Halt: This signal is used for platform boot halt. |