Intel^® Core™ Ultra 200S and 200HX Series Processor Datasheet, Volume 1 of 2

832586

Intel^® Core™ Ultra 200S and 200HX Series Processor Datasheet, Volume 2 of 2

834966

Intel^® Core™ Ultra 200H and 200U Series Processor Datasheet, Volume 1 of 2

842704

Intel^® Core™ Ultra 200H and 200U Series Processor Datasheet, Volume 2 of 2

844261

AP-485, Intel^® Processor Identification and the CPUID Instruction

Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture

Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M

Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set Reference Manual N-Z

Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide

Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System Programming Guide

Intel^® 64 and IA-32 Intel^® Architecture Optimization Reference Manual

Intel^® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes

Intel^® Virtualization Technology Specification for Directed I/O Architecture Specification

ACPI Specifications

This erratum is fixed or does not apply to the listed stepping or specification change does not apply to the listed stepping.

This erratum may be fixed in a future hardware stepping, firmware, or software update.

This erratum has been previously fixed in Intel hardware, firmware, or software.

There are no plans to fix this erratum.

Processor Line

S 8+16

S 6+8

HX

U

H

Single Step on Branches Might be Missed When VMM Enables Notification On VM Exit

Intel^® VT-d Remapping Hardware Does Not Perform Reserved(0) Check on PGSNP Field of Scalable-mode PASID Table Entry

N/A. Erratum has been removed.

MSI From VMD-Owned Device May Pass Memory Write

USB 3.2 Device May Not Function as Expected With TC10 Enabled

PCONFIG Error Reporting May be Incorrect

DP Monitor May Not Operate After S4/S5 Resume

PCIe Root Port Lane Error Status Register May Not be Cleared

Type-C Display May be Blank Following S3/S4/S5 Resume

Performance Monitoring Event Branch Instruction Retired Will Not Count CALLs to Next Sequential Instruction

Performance Monitoring Event Branch Instruction Retired Will Overcount on Certain Types of Branch and Complex Instructions

Processor Trace May Generate PSB Packets Too Infrequently

Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results

Architectural Performance Monitoring Events For Last Level Cache Will Overcount

Performance Monitoring Events TOPDOWN.BACKEND_​BOUND_​SLOTS and IDQ_​BUBBLES May be Inaccurate

Performance Monitoring Event IDQ.MS_​UOPS May Undercount

Performance Monitoring Event INT_​VEC_​RETIRED.MUL_​256 May Undercount

VM Exit Qualification May Not be Correctly Set on APIC Access While Serving a User Interrupt

PCIe REFCLK Inactive Prior to PERST#

Locked Page Split Access May Not be Detected by UC-lock Disable if Split-lock Disable is Not Used

Precision Time Measurement (PTM) Interpretation Capability Bit Incorrect Register Offset

Display Artifacts With YUV420 Format

Processor C-States With USB Full-Speed or Low-Speed Device Hotplug

xHCI Out of Order ACK Due to LCRD1

Non Canonical Fault May be Signaled on Access That Wraps Address Space When LAM is Enabled

Processor May Encrypt TME Exclude Range if Mapped to Remap Range

SPI0 Dual IO Mode With SPI0_​IO2 And SPI0_​IO3 Connected to SPI Device

Problem

Under complex micro-architectural conditions, single step on branches (IA32_​DEBUGCTLMSR (Offset 1D9h, bit [1]) and also TF flag in EFLAGS register is set) in guest might be missed when VMM enables notification on VM Exit (IA32_​VMX_​PROCBASED_​CTLS2 MSR, Offset 48Bh, bit [31]) while the dirty access bit is not set for the code page (bit [6] in paging-structure entry).

Implication

When single step is enabled under the above condition, some single step branches will be missed. Intel has only observed this erratum in a synthetic test environment.

Workaround

When enabling single step on branches for debugging, software should first set the dirty bit of the code page.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Intel^® VT-d remapping hardware does perform Reserved(0) check on Page Snoop (PGSNP) field in scalable-mode Process Address ID (PASID) table entry when Snoop Control capability is defined as not available in the Extended Capability Register Offset 10h bit 7 (ECAP.SC=0).

Implication

There are no known functional implications due to this erratum. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the storage subsystem is configured to operate in RAID 0 or 1 mode, a Message Signaled Interrupt (MSI) from an Intel^® Volume Management Device (Intel^® VMD) owned device may interrupt a core before a previous write from the device is completed.

Implication

Due to this erratum, the platform may experience unpredictable system behavior.

Workaround

None identified. The VMD MSI interrupt-handler should initially perform a dummy register read to the MSI initiator device prior to any writes to ensure proper PCIe ordering.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When TC10 is enabled, a USB 3.2 device connected to USB Type-C port directly without retimer may not function as expected.

Implication

Due to this erratum, a USB 3.2 device may not function as expected.

Workaround

None identified. It may be possible for the BIOS to contain a mitigation for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If invalid parameters are provided, the PCONFIG instruction should generate a #GP exception. Due to this erratum, the processor may instead set a ZF flag, with EAX reporting failure reasons.

Implication

Due to this erratum, incorrectly configured PCONFIG usage may lead to unexpected error reporting.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When switching a USB Type-C Display Port (DP) monitor connection between Alt Mode and MFD in S4/S5, the monitor may not be enumerated when resuming from S4/S5.

Implication

Due to this erratum, a DP Monitor may not operate when resuming from S4/S5 and may require a hot plug to recover.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Re-enabling a port following a link disable or hot reset the PCIe Lane Error Status register (Offset 0xA38) may not be cleared.

Implication

Due to this erratum, the Lane Error Status register may indicate lane errors on some of the Root Ports. Intel has not observed any functional issues due this erratum.

Workaround

None identified. Software should ignore the lane error status register to mitigate this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When switching between Type-C Display Alt Mode and a Multi-Function Device (MFD) while the system is in S3/S4/S5, the Display may not enumerate.

Implication

When this erratum occurs, the Display may be blank. A device unplug and re-plug may be necessary to recover the display.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A CALL instruction whose target is the next sequential instruction (the same address pushed onto the stack) will not increment the performance monitoring event BR_​INST_​RETIRED (Event: C4H, UMask: 00H, F9H).

Implication

Due to this erratum, software monitoring Branch Instruction Retired events may undercount. Since the CALL is to the next instruction, control flow tracing with the Last Branch Retired (LBR) records should not be affected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On certain types of branch and complex instructions, the performance monitoring event BR_​INST_​RETIRED (Event: C4H, UMask: 00H / 7EH / BFH / C0H / DFH / EBH / FBH / F9H) will overcount by 1. Affected instructions include FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD, and complex SGX/SMX/CSTATE instructions/flows.

Implication

Due to this erratum, software monitoring Branch Instruction Retired events may overcount.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A Packet Stream Boundary (PSB) packet should be generated for every PSBFreq number of trace output bytes. Due to this erratum, PSB packets may be generated only after as many as four times that number of output bytes have been generated.

Implication

Due to this erratum, trace decoder software may see fewer PSB packets than expected. This may lead to the trace decoder software needing to search further to find a starting point to decode or, when used in circular mode, being unable to decode the trace due to lacking any PSB packets.

Workaround

None identified. The software can request more frequent PSB packets by programming PSBFreq (bits[27:24]) of IA32_​RTIT_​CTL MSR (570H) to a value 1/4 of the desired value.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The act of one processor or system bus master writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing instruction prior to execution of the new code is called unsynchronized XMC.Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code.

Implication

In this case, the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide including a General Protection Fault (GPF) or other unexpected behaviors. In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system.

Workaround

In order to avoid this erratum programmers should use the XMC synchronization algorithm as detailed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide Section: Handling Self- and Cross-Modifying Code.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The Performance Monitoring Event LONGEST_​LAT_​CACHE.REFERENCES (Event: 2EH, UMask: 4FH) and LONGEST_​LAT_​CACHE.MISS (Event: 2EH, UMask: 41H) will double count.

Implication

Due to this erratum, software monitoring these two events for last level cache will observe counts that are two times the actual value.

Workaround

None identified. Software may mitigate this issue by dividing the counter value by two.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events TOPDOWN.BACKEND_​BOUND_​SLOTS (Event A4h, UMask 02h) and IDQ_​BUBBLES.* (Event 9Ch, UMask 01h) may not count when the processor is in the C0.2 power sub-state, which is entered via the TPAUSE or UWAIT instructions. This erratum also impacts the accuracy of MSR_​PERF_​METRICS fields Frontend Bound, Backend Bound, and Fetch Latency (MSR 329h, Bits [23:16], [31:24] and [55:48]).

Implication

Due to this erratum, these performance monitoring events and the fields in MSR_​PERF_​METRICS may be inaccurate.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events IDQ.MS_​UOPS, IDQ.MS_​SWITCHES, and IDQ.MS_​CYCLES_​ANY (Event 79h, UMask 30h) may undercount MS_​UOPS that come from the Decode Stream Buffer (DSB).

Implication

Due to this erratum, performance monitoring counters may report counts lower than expected.

Workaround

None identified. Performance monitoring event UOPS_​RETIRED.MS may be used instead.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring event INT_​VEC_​RETIRED.MUL_​256 (Event E7h, Umask 80h) may not count VPMULLQ instructions.

Implication

Due to this erratum, the performance monitoring event may report lower counts than expected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A VM Exit that occurs while the processor is serving a user interrupt in non-root mode should set the “asynchronous to instruction execution” bit in the Exit Qualification field in the Virtual Machine Control Structure (bit 16). However, if a VM Exit occurs during processing a user interrupt due to an APIC access, the bit will not be set.

Implication

Due to this erratum, the “asynchronous to instruction execution” bit will not be set if an APIC Access VM Exit occurs while the processor is serving a user interrupt. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

PCIe differential reference clocks may go inactive prior to the assertion of PERST#.

Implication

Due to this erratum, the PCI Express® Card Electromechanical Specification, Revision 5.0, Version 1.0 Power Section 2.2.2 "Management States (S0 to S3/S4 to S0)" requirement is not followed. Intel has not observed any functional implications due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The UC-lock disable feature (MSR_​MEMORY_​CTRL bit [28] (MSR 33h)) may not cause a fault (#AC(4)) for a page split lock that accesses a page with non-WB memory type if the split lock disable (MSR_​MEMORY_​CTRL bit [29]) is not set.

Implication

Due to this erratum, system software may not be able to fully prevent bus locks due to locks to non-WB memory unless they use the split-lock disable feature to prevent bus locks due to splits. Intel has not observed this erratum with any commercially available software.

Workaround

None identified. Software using the UC-lock disable feature should also enable the split lock disable feature.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The PTM Propagation Delay Adaptation Interpretation B (PTMPDAIB) Bit is implemented at Configuration Space (CFG) Offset 158h instead of at 50h as documented in the PCI-SIG PTM Byte Ordering Adaptation Engineering Change Notice (ECN).

Implication

End Point Device (EPD) software that implements the PTM Byte Ordering Adaptation ECN will not be able to program their PTMPDAIB Bit correctly since it is located at a different register offset.

Workaround

None identified. To mitigate this issue, EPD software that implements the PTM Byte Ordering Adaptation ECN must access PTMPDAIB at CFG Offset 158h.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

While in DP2.1 UHBR mode and using the YUV420 format with scaling, displays with a resolution higher than 5K @ 60Hz may show display artifacts.

Implication

Due to this erratum, display artifacts may be seen.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When doing a hotplug on a USB hub with two or more USB Full-speed or Low-speed devices each with a 1 ms service interval interrupt endpoint, a race condition may occur between the PMC and the xHCI controller.

Implication

The processor may fail to enter C3 or deeper package C-States. Note: This erratum has only been observed in a synthetic environment.

Workaround

None identified. This condition is recovered after the xHCI controller has successfully entered D3.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A delay in the availability of LCRD1 (Link Credit 1) from a USB 3.2 hub, with two or more downstream USB 3.2 bulk endpoint devices engaged in SuperSpeedPlus concurrent transfers, may lead to the connected xHCI controller sending the ACK and Status of a transfer packet out of order.

Implication

Due to this erratum, a USB 3.2 bulk endpoint device may not respond to subsequent transfers. It may be possible for a device driver to recover the USB 3.2 device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When Linear Address Masking (LAM) is enabled, a non-canonical fault may be signaled if there is an access which splits the 64-bit linear address space (and thus touches both linear address FFFF_​FFFF_​FFFF_​FFFFh and 0h).

Implication

Due to this erratum, software may receive an unexpected exception on such accesses. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor accesses to TME exclude range may be encrypted but not decrypted if mapped to remap range.

Implication

Due to this erratum, the processor exclude range it will be encrypted but will but not decrypted if mapped to remap range.

Workaround

It may be possible for BIOS to workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On systems with dual IO mode enabled, SPI0_​IO2 and SPI0_​IO3 may momentarily drive low before these signals are pulled high by internal resistors during boot from the G3 state.

Implication

Due to this erratum, unexpected system behavior may occur on systems when SPI0_​IO2 and SPI0_​IO3 signals are connected to an SPI device.

Workaround

None identified. To mitigate this erratum, do not connect SPI0_​IO2 and SPI0_​IO3 to an SPI device in SPI0 dual IO mode enabled systems.

Status

For the steppings affected, refer to the Summary Table of Changes.