Summary Tables of Changes

Intel® Core™ Ultra 200V Series Processors

Specification Update

ID	Date	Version	Classification
827538	09/01/2026		Public

The following tables indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes which apply to the listed processor stepping. Intel may intend to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted. These tables use the following notations:

Codes Used in Summary Table

Stepping	Description
(No mark) or (Blank box)	This erratum is fixed or does not apply to the listed stepping or specification change does not apply to the listed stepping.

Status	Description
Plan Fix	This erratum may be fixed in a future hardware stepping, firmware, or software update.
Fixed	This erratum has been previously fixed in Intel hardware, firmware, or software.
No Fix	There are no plans to fix this erratum.

Errata Summary Table

Erratum ID	Processor Line	Title
Erratum ID	V 4P+4E	Title
LNL001	No Fix	xHCI USB 2.0 ISOCH Device Missed Service Interval
LNL002	No Fix	Intel^® VT-d Remapping Hardware Does Not Perform Reserved(0) Check on PGSNP Field of Scalable-mode PASID Table Entry
LNL003	No Fix	PCONFIG Error Reporting May be Incorrect
LNL004	No Fix	Remapping Hardware May Not Generate a Page Request Group Response Message While Operating in Legacy Mode or Abort DMA Mode
LNL005	N/A	N/A. Erratum ID updated to LNL017.
LNL006	No Fix	xHCI Controller Reset Due to Missing Link Credit From Device
LNL007	No Fix	Type-C Display May be Blank Following S3/S4/S5 Resume
LNL008	No Fix	Performance Monitoring Event Branch Instruction Retired Will Not Count CALLs to Next Sequential Instruction
LNL009	No Fix	Performance Monitoring Event Branch Instruction Retired Will Overcount on Certain Types of Branch and Complex Instructions
LNL010	No Fix	Processor Trace May Generate PSB Packets Too Infrequently
LNL011	No Fix	Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results
LNL012	N/A	N/A. Erratum has been removed.
LNL013	No Fix	Performance Monitoring Events TOPDOWN.BACKEND_BOUND_SLOTS and IDQ_BUBBLES May be Inaccurate
LNL014	No Fix	Performance Monitoring Event IDQ.MS_UOPS May Undercount
LNL015	No Fix	Performance Monitoring Event INT_VEC_RETIRED.MUL_256 May Undercount
LNL016	No Fix	Processor May Encrypt TME Exclude Range if Mapped to Remap Range
LNL017	No Fix	Non-Responsive USB Port After Disconnecting Full-speed Device
LNL018	No Fix	Incorrect NPU MSI Pending Register Value
LNL019	No Fix	Processor C-States With USB Full-Speed or Low-Speed Device Hotplug
LNL020	No Fix	USB 3.2 Gen 1x1 Port Does Not Send 16 Polling LFPS Burst
LNL021	No Fix	xHCI Out of Order ACK Due to LCRD1
LNL022	No Fix	Unexpected Graphics Behavior With Graphics Memory Bandwidth Compression
LNL023	Fixed	Unexpected Global Reset During Microcode Update
LNL024	Fixed	System Hang From Frequent Audio Starts/Stops
LNL025	No Fix	SPI0 Dual IO Mode With SPI0_IO2 And SPI0_IO3 Connected to SPI Device
LNL026	No Fix	Display Artifacts With YUV420 Format
LNL027	No Fix	Locked Page Split Access May Not be Detected by UC-lock Disable if Split-lock Disable is Not Used
LNL028	Fixed	System Hang With Concurrent Workloads
LNL029	No Fix	USB 3.2 Device May Not Function as Expected With TC10 Enabled
LNL030	Fixed	Monitor Hit May Not Wake P-cores From Power State Core C6
LNL031	Fixed	xHCI Host Termination During U3 Link Exit
LNL032	No Fix	Cache Level Wrongly Reported in Machine Check Banks
LNL033	Fixed	Incorrect Core TLB Entry May be Retrieved Following VM Exit
LNL034	Fixed	Unexpected Global Reset or PCODE_INTERNAL_ERROR Machine Check With pCode 2.6.10
LNL035	N/A	N/A. Erratum has been removed.
LNL036	Fixed	Machine Check PUNIT_INTERNAL_ERROR During Sx/S0ix Entry
LNL037	Fixed	Processor SRAM Transactions May Not Complete
LNL038	Fixed	RDTSC Instructions May Return Non-Incremental Value
LNL039	Fixed	PMIC SVID Alert Signal Not De-asserted Following VR Thermal Event
LNL040	Fixed	Unexpected Processor Throttling When Exceeding DRAM Maximum Temperature Threshold
LNL041	Fixed	IA32_HWP_STATUS MSR May be Cleared
LNL042	Fixed	Unpredictable System Behavior May Occur When C6 or Deeper Sleep States Are Used
LNL043	Fixed	A Core May Hang When Entering or Exiting C6 or Deeper Sleep States
LNL044	N/A	N/A. Erratum has been removed.
LNL045	Fixed	Indirect Branches May Cause Execution of Incorrect Instructions
LNL046	Planned Fix	System Hang or System Hang With Internal Timer Machine Check Exception (400h) Following a Core C1 Exit
LNL047	Fixed	REP SCASB or REP CMPSB Instructions May Return Incorrect Results
LNL048	No Fix	Performance Monitoring Event For Memory Bound Stalls May Undercount
LNL049	No Fix	USB 2.0 Isochronous Missed Service Interval With Concurrent Bulk Traffic and Package C-States
LNL050	Fixed	USB 3.2 Bulk Transfers After Device Initiated Flow Control
LNL051	No Fix	Intel^® PT Incorrect CR3-Filtering
LNL052	No Fix	Incorrect Last Branch From Value in BTS Branch Record During a Task Switch
LNL053	No Fix	xHCI Unresponsive Due to Split Transaction Error
LNL054	No Fix	Performance Monitoring Event MEMORY_ACTIVITY.STALLS_L2_MISS May Undercount
LNL055	No Fix	Performance Monitoring Event MEMORY_STALLS.L2 May Overcount
LNL056	No Fix	Timed PEBS Retire Latency Field May be Incorrect
LNL057	No Fix	Remapping Hardware Does Not Perform a Reserved(0) Check in Interrupt Remap Table Entry
LNL058	No Fix	USB DbC or Device Mode Port When Exiting S4, S5, or G3
LNL059	No Fix	Certain VMCS Fields May be Incorrect During STM to VMX Transitions
LNL060	No Fix	Certain BR_MISP_RETIRED Performance Monitoring Events May Overcount
LNL061	No Fix	LBR Event Logging IA32_LBR_x_INFO.PMCx_CNT Field May Undercount
LNL062	No Fix	Bandwidth Allocation for USB 2.0 Periodic Devices Behind USB 3.2 Hub
LNL063	No Fix	Instruction Timeout VM Exit Will Not Set Guest RFLAGS.RF During #UD
LNL064	No Fix	Debug Exceptions May Be Lost or Misreported When MOV SS or POP SS Instruction is Not Followed By a Write to SP
LNL065	No Fix	I3C Interface Minimum Clock Timing Specifications
LNL066	No Fix	ICR Read May Not Generate an APIC‑Access VM Exit
LNL067	No Fix	IAA Decompression Logic May Return Non-Deterministic Value of Bytes Completed in Completion Record
LNL068	No Fix	Intel^® PT Event Trace Generates CFE and FUP After VMCS/PIP Packets During VM Entry
LNL069	No Fix	Intel^® PT Event Trace Generates Incorrect IP for FUP Packet During VM Entry
LNL070	No Fix	Incorrect Guest RFLAGS.RF on VM Entry
LNL071	Fixed	Execution of IRET in Compatibility Mode May Free Supervisor Shadow Stack Token
LNL072	No Fix	Incorrect VM Exit Reason When MOV SS or POP SS Followed by an x2APIC MSR Access

Specification Changes

No.	Specification Changes
	None for this revision of this specification update.

Specification Clarifications

No.	Specification Clarifications
	None for this revision of this specification update.

Documentation Changes

No.	Documentation Changes
	None for this revision of this specification update.