Intel® Core™ Ultra Processor

Datasheet, Volume 1 of 2
Supporting Intel® Core™ Ultra Processor for U/H-series Platforms, formerly known as Meteor Lake

ID Date Version Classification
792044 12/15/2023 Public

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Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Processor and Device IDs Package Mechanical Specifications Memory Mapping Security Technologies Intel® Virtualization Technology (Intel® VT) Platform Environmental Control Interface (PECI) Intel® Image Processing Unit (Intel® IPU6) Intel® Neural Processing Unit (Intel® NPU) Audio Voice and Speech Power Management Power Delivery Electrical Specifications Thermal Management System Clocks Real Time Clock (RTC) Memory USB Type-C* Sub System Universal Serial Bus (USB) PCI Express* (PCIe*) Serial ATA (SATA) Intel® Volume Management Device (Intel® VMD) Technology Graphics Display Processor Sideband Signals General Purpose Input and Output Interrupt Timer Subsystem (ITSS) GPIO Serial Expander Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers Gigabit Ethernet Controller Connectivity Integrated (CNVi) Controller Link Integrated Sensor Hub (ISH) System Management System Management Interface and SMLink Host System Management Bus (SMBus) Controller Serial Peripheral Interface (SPI) Enhanced Serial Peripheral Interface (eSPI) Intel® Serial IO Generic SPI (GSPI) Controllers Touch Host Controller (THC) Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Private Configuration Space Port ID Testability and Monitoring Miscellaneous Signals
Legal Disclaimer
Revision History
Introduction
Introduction Processor Volatility Statement Package Support Supported Technologies Power Management Support Thermal Management Support Ballout Information Processor Testability Operating Systems Support Terminology and Special Marks Flexible High Speed I/O Related Documents
Processor Volatility Statement
Package Support
U/H Processors Package Support
U/H Processors Package Support
Supported Technologies
Supported Technologies API Support (Windows*) Firmware Resiliency
API Support (Windows*)
Firmware Resiliency
Power Management Support
Power Management Support Processor Core Power Management System Power Management Memory Controller Power Management Processor Graphics Power Management
Processor Core Power Management
System Power Management
Memory Controller Power Management
Processor Graphics Power Management
Thermal Management Support
Ballout Information
Processor Testability
Operating Systems Support
Terminology and Special Marks
Flexible High Speed I/O
Flexible High Speed I/O Processor-U Processor-H
Processor-U
Processor-H
Related Documents
Processor and Device IDs
Processor and Device IDs CPUID PCI Configuration Header Device IDs Revision IDs
CPUID
PCI Configuration Header
Device IDs
Revision IDs
Package Mechanical Specifications
Package Mechanical Specifications Package Mechanical Attributes Package Loading and Tile Pressure Specifications Package Storage Specifications
Package Mechanical Attributes
Package Loading and Tile Pressure Specifications
Package Loading and Tile Pressure Specifications Static Compressive Load Specification Maximum Pressure Specifications
Static Compressive Load Specification
Maximum Pressure Specifications
Package Storage Specifications
Memory Mapping
Memory Mapping Functional Description Memory Map
Functional Description
PCI Devices and Functions Fixed I/O Address Ranges Variable I/O Decode Ranges
PCI Devices and Functions
Fixed I/O Address Ranges
Variable I/O Decode Ranges
Memory Map
Memory Map Boot Block Update Scheme
Boot Block Update Scheme
Security Technologies
Security Technologies Intel® Converged Boot Guard and Intel® TXT Crypto Acceleration Instructions Intel® Secure Key Execute Disable Bit Intel® Supervisor Mode Execution Prevention (Intel® SMEP) Intel® Supervisor Mode Access Prevention (Intel® SMAP) User Mode Instruction Prevention (UMIP) Read Processor ID (RDPID) Intel® Total Memory Encryption - Multi-Key Control-flow Enforcement Technology (Intel® CET) KeyLocker Technology Intel® Hardware Shield BIOS Guard Intel® Platform Trust Technology Linear Address Space Separation (LASS) Security Firmware Engines
Intel® Converged Boot Guard and Intel® TXT
Crypto Acceleration Instructions
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) New Cryptographic Acceleration Instructions
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
New Cryptographic Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Prevention (Intel® SMEP)
Intel® Supervisor Mode Access Prevention (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
Control-flow Enforcement Technology (Intel® CET) Shadow Stack Indirect Branch Tracking
Shadow Stack
Indirect Branch Tracking
KeyLocker Technology
Intel® Hardware Shield
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Security Firmware Engines
Intel® Converged Security and Management Engine (Intel® CSME) Intel® Silicon Security Engine Intel® Graphics System Controller (Intel® GSC)
Intel® Converged Security and Management Engine (Intel® CSME)
Intel® Silicon Security Engine
Intel® Graphics System Controller (Intel® GSC)
Intel® Virtualization Technology (Intel® VT)
Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x) Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Intel® APIC Virtualization Technology (Intel® APICv) Hypervisor-Managed Linear Address Translation (HLAT)
Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x)
Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)
Intel® APIC Virtualization Technology (Intel® APICv)
Hypervisor-Managed Linear Address Translation (HLAT)
Platform Environmental Control Interface (PECI)
Platform Environmental Control Interface (PECI) PECI Bus Architecture
PECI Bus Architecture
Intel® Image Processing Unit (Intel® IPU6)
Platform Imaging Infrastructure Intel® Image Processing Unit (Intel® IPU6) Camera/MIPI
Platform Imaging Infrastructure
Intel® Image Processing Unit (Intel® IPU6)
Camera/MIPI
Camera/MIPI Camera Pipe Support MIPI* CSI-2 Camera Interconnect
Camera Pipe Support
MIPI* CSI-2 Camera Interconnect
MIPI* CSI-2 Camera Interconnect Camera Control Logic Camera Modules MIPI* CSI-2 Interface Signals
Camera Control Logic
Camera Modules
MIPI* CSI-2 Interface Signals
Intel® Neural Processing Unit (Intel® NPU)
Intel® Neural Processing Unit (Intel® NPU) Functional Description
Functional Description
Functional Description Processor Subsystem NCE Subsystem
Processor Subsystem
NCE Subsystem
NCE Subsystem Some NCE Subsystem Features NCE Tile ACT-SHAVE
Some NCE Subsystem Features
NCE Tile
ACT-SHAVE
Audio Voice and Speech
Audio Voice and Speech Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Audio DSP Capabilities Intel® High Definition Audio Interface Capabilities Direct Attached Digital Microphone (PDM) Interface USB Audio Offload Support I2S / PCM Interface Intel® Display Audio Interface MIPI® SoundWire* Interface Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S / PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Power Management
Power Management System Power States, Advanced Configuration and Power Interface (ACPI) Legacy Power Management Support Functional Description Processor IA Core Power Management Processor Graphics Power Management TCSS Power State Power and Performance Technologies Deprecated Technology Power and Internal Signals
System Power States, Advanced Configuration and Power Interface (ACPI)
Legacy Power Management Support
ALT Access Mode Legacy Power Management Theory of Operation
ALT Access Mode
Legacy Power Management Theory of Operation
Functional Description
Features Power Saving Features SMI#/SCI Generation Sleep States Event Input Signals and Their Usage System Power Supplies, Planes, and Signals Reset Behavior
Features
Power Saving Features
SMI#/SCI Generation
Sleep States
Event Input Signals and Their Usage
System Power Supplies, Planes, and Signals
Reset Behavior
Processor IA Core Power Management
Processor IA Core Power Management OS/HW Controlled P-states Low-Power Idle States Requesting the Low-Power Idle States Processor IA Core C-State Rules Package C-States Package C-States and Display Resolutions
OS/HW Controlled P-states
Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Low-Power Idle States
Requesting the Low-Power Idle States
Processor IA Core C-State Rules
Package C-States
Package C-States and Display Resolutions
Processor Graphics Power Management
Processor Graphics Power Management Memory Power Savings Technologies Display Power Savings Technologies Processor Graphics Core Power Savings Technologies
Memory Power Savings Technologies
Display Power Savings Technologies
Processor Graphics Core Power Savings Technologies
TCSS Power State
Power and Performance Technologies
Power and Performance Technologies Intel® Smart Cache Technology P-core, E-core, and LP E-core Level 1 and Level 2 Caches Ring Interconnect Intel® Hybrid Technology Intel® Turbo Boost Max Technology 3.0 Intel® Hyper-Threading Technology (Intel® HT Technology) Intel® Turbo Boost Technology 2.0 System Agent Enhanced Intel SpeedStep® Technology Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® 64 Architecture x2APIC Intel® Transactional Synchronization Extensions (Intel ®TSX-NI) Intel® Dynamic Tuning Technology (Intel® DTT) Intel® GMM and Neural Network Accelerator (Intel® GNA 3.0) Cache Line Write Back (CLWB) Remote Action Request (RAR) User Mode Wait Instructions
Intel® Smart Cache Technology
P-core, E-core, and LP E-core Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Max Technology 3.0
Intel® Hyper-Threading Technology (Intel® HT Technology)
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Technology 2.0 Intel® Turbo Boost Technology 2.0 Power Monitoring Intel® Turbo Boost Technology 2.0 Power Control Intel® Turbo Boost Technology 2.0 Frequency
Intel® Turbo Boost Technology 2.0 Power Monitoring
Intel® Turbo Boost Technology 2.0 Power Control
Intel® Turbo Boost Technology 2.0 Frequency
System Agent Enhanced Intel SpeedStep® Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® AVX2 Vector Neural Network Instructions (AVX2 VNNI)
Intel® AVX2 Vector Neural Network Instructions (AVX2 VNNI)
Intel® 64 Architecture x2APIC
Intel® Transactional Synchronization Extensions (Intel ®TSX-NI)
Intel® Dynamic Tuning Technology (Intel® DTT)
Intel® GMM and Neural Network Accelerator (Intel® GNA 3.0)
Cache Line Write Back (CLWB)
Remote Action Request (RAR)
User Mode Wait Instructions
Deprecated Technology
Power and Internal Signals
Signal Description Power Sequencing Signals Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Power Sequencing Signals
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Power Delivery
Power and Ground Signals Digital Linear Voltage Regulator (DLVR) Fast V-Mode (FVM) Current Excursion Protection (CEP) Reactive PL4 with PL4 Boost
Power and Ground Signals
Digital Linear Voltage Regulator (DLVR)
Fast V-Mode (FVM)
Current Excursion Protection (CEP)
Reactive PL4 with PL4 Boost
Electrical Specifications
Electrical Specifications Processor Power Rails
Processor Power Rails
Processor Power Rails Power and Ground Pins Voltage Regulator VCC Voltage Identification (VID)
Power and Ground Pins
Voltage Regulator
VCC Voltage Identification (VID)
Thermal Management
Processor Thermal Management Processor Base Power Thermal and Power Specifications Processor Line Thermal and Power Specifications Error and Thermal Protection Signals Thermal Sensor
Processor Thermal Management
Processor Thermal Management Thermal Considerations Thermal Management Features Assured Power (cTDP) Intel® Memory Thermal Management
Thermal Considerations
Thermal Considerations Package Power Control Platform Power Control Turbo Time Parameter (Tau)
Package Power Control
Platform Power Control
Turbo Time Parameter (Tau)
Thermal Management Features
Thermal Management Features Adaptive Thermal Monitor Digital Thermal Sensor PROCHOT# Signal PROCHOT Output Only Bi-Directional PROCHOT# PROCHOT Demotion Voltage Regulator Protection using PROCHOT# Thermal Solution Design and PROCHOT# Behavior Low-Power States and PROCHOT# Behavior THRMTRIP# Signal Critical Temperature Detection Software Controlled Clock Modulation (On-Demand Mode)
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
Software Controlled Clock Modulation (On-Demand Mode)
Assured Power (cTDP)
Assured Power (cTDP) Assured Power (cTDP) Modes Low Power Mode
Assured Power (cTDP) Modes
Low Power Mode
Intel® Memory Thermal Management
Processor Base Power Thermal and Power Specifications
Processor Line Thermal and Power Specifications
Error and Thermal Protection Signals
Thermal Sensor
Thermal Sensor Modes of Operation Temperature Trip Point Thermal Sensor Accuracy (Taccuracy) Thermal Reporting to EC Thermal Trip Signal (SOCHOT#)
Modes of Operation
Temperature Trip Point
Thermal Sensor Accuracy (Taccuracy)
Thermal Reporting to EC
Thermal Trip Signal (SOCHOT#)
System Clocks
System Clocks Integrated Clock Controller (ICC) I/O Signal Pin States Clock Topology
Integrated Clock Controller (ICC)
Integrated Clock Controller (ICC) Signal Description
Signal Description
I/O Signal Pin States
Clock Topology
Clock Topology Integrated Reference Clock PLL
Integrated Reference Clock PLL
Real Time Clock (RTC)
Real Time Clock (RTC) Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Memory
Memory System Memory Interface Integrated Memory Controller (IMC) Power Management Signal Description
System Memory Interface
System Memory Interface Processor SKU Support Matrix Supported Memory Modules and Devices System Memory Timing Support Memory Controller (MC) System Memory Controller Organization Mode System Memory Frequency Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling Data Swapping LPDDR5/x CMD/ADD Ascending and Descending DDR I/O Interleaving DRAM Clock Generation DRAM Reference Voltage Generation Data Swizzling Error Correction With Standard RAM Post Package Repair (PPR)
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
System Memory Timing Support SAGV Points
SAGV Points
Memory Controller (MC)
System Memory Controller Organization Mode
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
LPDDR5/x CMD/ADD Ascending and Descending
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
Integrated Memory Controller (IMC) Power Management
Integrated Memory Controller (IMC) Power Management Disabling Unused System Memory Outputs DRAM Power Management and Initialization DDR Electrical Power Gating Power Training
Disabling Unused System Memory Outputs
DRAM Power Management and Initialization
DRAM Power Management and Initialization Conditional Self-Refresh Dynamic Power-Down DRAM I/O Power Management
Conditional Self-Refresh
Dynamic Power-Down
DRAM I/O Power Management
DDR Electrical Power Gating
Power Training
Signal Description
USB Type-C* Sub System
USB Type-C* Sub System General Capabilities USB* 4 Router xHCI/xDCI Controllers Display Interface USB Type-C Signals AUX BIAS Control
General Capabilities
USB* 4 Router
USB* 4 Router USB 4 Host Router Implementation Capabilities
USB 4 Host Router Implementation Capabilities
xHCI/xDCI Controllers
xHCI/xDCI Controllers USB 3 Controllers PCIe Interface
USB 3 Controllers
USB 3 Controllers Extensible Host Controller Interface (xHCI) Extensible Device Controller Interface (xDCI)
Extensible Host Controller Interface (xHCI)
Extensible Device Controller Interface (xDCI)
PCIe Interface
Display Interface
USB Type-C Signals
AUX BIAS Control
Universal Serial Bus (USB)
Universal Serial Bus (USB) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Supported USB 2.0 Ports
Functional Description
eXtensible Host Controller Interface (xHCI) Controller USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
eXtensible Host Controller Interface (xHCI) Controller
USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Supported USB 2.0 Ports
PCI Express* (PCIe*)
PCI Express* (PCIe*) Functional Description Signal Description I/O Signal Planes and States PCI Express* Root Port Support Feature Details
Functional Description
Functional Description PCI Express* Power Management Port 80h Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single - Root I/O Virtualization (SR - IOV) PCI Express* Receiver Lane Polarity Inversion Precision Time Measurement (PTM)
PCI Express* Power Management
Port 80h Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
PCI Express* Receiver Lane Polarity Inversion
Precision Time Measurement (PTM)
Signal Description
I/O Signal Planes and States
PCI Express* Root Port Support Feature Details
Serial ATA (SATA)
Serial ATA (SATA) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Features Supported SATA 6 Gb/s Support Hot Plug Operation Intel® Rapid Storage Technology (Intel® RST) Power Management Operation SATA Device Presence SATA LED Advanced Host Controller Interface (AHCI) Operation
Features Supported
SATA 6 Gb/s Support
Hot Plug Operation
Intel® Rapid Storage Technology (Intel® RST)
Power Management Operation
SATA Device Presence
SATA LED
Advanced Host Controller Interface (AHCI) Operation
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Volume Management Device (Intel® VMD) Technology
Graphics
Graphics Processor Graphics Platform Graphics Hardware Feature
Processor Graphics
Processor Graphics Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD) Hardware Accelerated Video Decode Hardware Accelerated Video Encode Hardware Accelerated Video Processing Hardware Accelerated Transcoding
Hardware Accelerated Video Decode
Hardware Accelerated Video Encode
Hardware Accelerated Video Processing
Hardware Accelerated Transcoding
Platform Graphics Hardware Feature
Platform Graphics Hardware Feature Hybrid Graphics
Hybrid Graphics
Display
Display Display Technologies Support Display Interfaces Display Features
Display Technologies Support
Display Interfaces
Display Interfaces Digital Display Interface DDI Signals Digital Display Interface TCP Signals
Digital Display Interface DDI Signals
Digital Display Interface TCP Signals
Display Features
Display Features General Capabilities Multiple Display Configurations High-bandwidth Digital Content Protection (HDCP) DisplayPort* High-Definition Multimedia Interface (HDMI*) embedded DisplayPort* (eDP*) Integrated Audio
General Capabilities
Multiple Display Configurations
High-bandwidth Digital Content Protection (HDCP)
DisplayPort*
DisplayPort* Multi-Stream Transport (MST)
Multi-Stream Transport (MST)
High-Definition Multimedia Interface (HDMI*)
embedded DisplayPort* (eDP*)
Integrated Audio
Processor Sideband Signals
Processor Sideband Signals Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
General Purpose Input and Output
General Purpose Input and Output Functional Description Signal Description
Functional Description
Functional Description Interrupt / IRQ via GPIO Requirement Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO GPIO Blink (BK) and Serial Blink (SBK) GPIO Ownership Native Function and TERM Bit Setting
Interrupt / IRQ via GPIO Requirement
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Signal Description
Interrupt Timer Subsystem (ITSS)
Interrupt Timer Subsystem (ITSS) Feature Overview Functional Description
Feature Overview
Functional Description
Functional Description 8254 Timers APIC Advanced Interrupt Controller High Precision Event Timer (HPET)
8254 Timers
8254 Timers Timer Programming Reading from Interval Timer
Timer Programming
Reading from Interval Timer
APIC Advanced Interrupt Controller
High Precision Event Timer (HPET)
High Precision Event Timer (HPET) Timer Accuracy Timer Off-load Periodic Versus Non-Periodic Modes Enabling the Timers Interrupt Levels
Timer Accuracy
Timer Off-load
Periodic Versus Non-Periodic Modes
Enabling the Timers
Interrupt Levels
GPIO Serial Expander
GPIO Serial Expander Functional Description Signal Description Integrated Pull-ups and Pull-downs
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Protocols Overview DMA Controller Reset Power Management Interrupts Error Handling Programmable SDA Hold Time
Protocols Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Programmable SDA Hold Time
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Reset Power Management Interrupts
Reset
Power Management
Interrupts
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Gigabit Ethernet Controller
Gigabit Ethernet Controller Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description GbE PCI Bus Interface Error Events and Error Reporting Ethernet Interface PCI Power Management
GbE PCI Bus Interface
Error Events and Error Reporting
Ethernet Interface
PCI Power Management
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Connectivity Integrated (CNVi)
Connectivity Integrated (CNVi) Functional Description Signal Description Integrated Pull-ups and Pull-downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
I/O Signal Planes and States
Controller Link
Controller Link Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States External CL_RST# Pin Driven/Open-drained Mode Support
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
External CL_RST# Pin Driven/Open-drained Mode Support
Integrated Sensor Hub (ISH)
Integrated Sensor Hub (ISH) Features Functional Description Signal Description Integrated Pull-Ups and Pull-Down I/O Signal Planes and States
Features
ISH I2C Controllers ISH UART Controller ISH GSPI Controller ISH GPIOs
ISH I2C Controllers
ISH UART Controller
ISH GSPI Controller
ISH GPIOs
Functional Description
Functional Description ISH Micro-Controller SRAM PCI Host Interface ISH IPC ISH Interrupt Handling via IOAPIC (Interrupt Controller)
ISH Micro-Controller
SRAM
PCI Host Interface
ISH IPC
ISH Interrupt Handling via IOAPIC (Interrupt Controller)
Signal Description
Integrated Pull-Ups and Pull-Down
I/O Signal Planes and States
System Management
System Management Theory of Operation
Theory of Operation
Theory of Operation TCO Modes
TCO Modes
System Management Interface and SMLink
System Management Interface and SMLink Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Integrated USB-C* Usage
Integrated USB-C* Usage
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Host System Management Bus (SMBus) Controller
Host System Management Bus (SMBus) Controller Functional Description SMBus Power Gating Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Host Controller SMBus Target Interface
Host Controller
SMBus Target Interface
SMBus Power Gating
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
SPI0 for Flash SPI0 Support for TPM
SPI0 for Flash
SPI0 Support for TPM
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Operating Frequency WAIT States from eSPI device In-Band Link Reset Flash Sharing Mode PECI Over eSPI Multiple OOB processes Channels and Supported Transactions
Operating Frequency
WAIT States from eSPI device
In-Band Link Reset
Flash Sharing Mode
PECI Over eSPI
Multiple OOB processes
Channels and Supported Transactions
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial IO Generic SPI (GSPI) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Controller Overview DMA Controller Reset Power Management Interrupts Error Handling
Controller Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Touch Host Controller (THC)
Touch Host Controller (THC) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States LSx
Functional Description
UART Serial (RS-232) Protocols Overview 16550 8-bit Addressing - Debug Driver Compatibility DMA Controller Reset Power Management Interrupts Error Handling
UART Serial (RS-232) Protocols Overview
16550 8-bit Addressing - Debug Driver Compatibility
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
LSx
LSx LSx Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
LSx Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Private Configuration Space Port ID
Testability and Monitoring
Testability and Monitoring Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Miscellaneous Signals
Signal Description Integrated Pull-Ups and Pull-Downs Ground and Reserved Signals
Signal Description
Integrated Pull-Ups and Pull-Downs
Ground and Reserved Signals

Boot Block Update Scheme

The Processor supports a “Top-Block Swap” mode that has the Processor swap the top block in the SPI flash (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the “top-swap” enable bit is set, the Processor will invert A16 for cycles going to the upper two 64-KB blocks in the appropriate address lines.

For SPI when top swap is enabled, the behavior is as described below. When the Top Swap Enable bit is 0, the Processor will not invert any address bit.

Boot Block Update Scheme

BOOT_​BLOCK_​SIZE Value

Accesses to

Being Directed to

000 (64KB)

FFFF_​0000h - FFFF_​FFFFh

FFFE_​0000h - FFFE_​FFFFh and vice versa

001 (128KB)

FFFE_​0000h - FFFF_​FFFFh

FFFC_​0000h - FFFD_​FFFFh and vice versa

010 (256KB)

FFFC_​0000h - FFFF_​FFFFh

FFF8_​0000h - FFFB_​FFFFh and vice versa

011 (512KB)

FFF8_​0000h - FFFF_​FFFFh

FFF0_​0000h - FFF7_​FFFFh and vice versa

100 (1MB)

FFF0_​0000h - FFFF_​FFFFh

FFE0_​0000h - FFEF_​FFFFh and vice versa

101 - 111

Reserved

Reserved

Note:This bit is automatically set to 0 by RTCRST#, but not by PLTRST#.

The scheme is based on the concept that the top block is reserved as the “boot” block, and the block immediately below the top block is reserved for doing boot-block updates.

The algorithm is:

  1. Software copies the top block to the block immediately below the top
  2. Software checks that the copied block is correct. This could be done by performing a checksum calculation.
  3. Software sets the “Top-Block Swap” bit. This will invert the appropriate address bits for the cycles going to the SPI.
  4. Software erases the top block
  5. Software writes the new top block
  6. Software checks the new top block
  7. Software clears the top-block swap bit
  8. Software sets the Top_​Swap Lock-Down bit

If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the top-swap bit is backed in the RTC well.

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