P-core, E-core, and LP E-core Level 1 and Level 2 Caches

The 1st level caches are not shared between physical cores and each physical core has a separate set of caches.

The P-Core 1st level cache hierarchy is divided into:

• A Data Cache (DL1)
• An Instruction Cache (IL1)

On the data side, it is built as one-level cache, with L1 of 48KB, 12-way set-associative.

On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.

The E-Core 1st level cache hierarchy is divided into:

• A Data Cache (DL1)
• An Instruction Cache (IL1)

On the data side, it is built as one-level cache, with L1 of 32KB, 8-way set-associative.

On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.

The LP E-Core 1st level cache hierarchy is divided into:

• A Data Cache (DL1)
• An Instruction Cache (IL1)

On the data side, it is built as one-level cache, with L1 of 32KB, 8-way set-associative.

On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.

The 2nd level cache holds both data and instructions. It is also referred to as mid-level cache or MLC.

• The P-core 2nd level caches are not shared between physical cores and each physical core has a separate set of caches. Its size is 2MB and it is a 16-way associative non-inclusive cache.
• The E-core 2nd level cache is shared between E-Cores within a module of 4 E-Cores in the Compute tile. Its size is 2MB and it is a 16-way associative non-inclusive cache.
• The LP E-core 2nd level cache is shared between LP E-Cores within a module of 2 LP E-Cores in the SOC tile. Its size is 2MB and it is a 16-way associative non-inclusive cache.