Intel® Core™ Ultra Processor
Datasheet, Volume 1 of 2
Supporting Intel® Core™ Ultra Processor for U/H/U-Type4-series Platforms, formerly known as Meteor Lake
| ID | Date | Version | Classification |
|---|---|---|---|
| 792044 | 05/09/2025 | Public |
Legal Disclaimer
Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
Memory Mapping
Security Technologies
Intel® Virtualization Technology (Intel® VT)
Platform Environmental Control Interface (PECI)
Intel® GMM and Neural Network Accelerator (Intel® GNA 3.0)
Intel® Image Processing Unit (Intel® IPU6)
Intel® Neural Processing Unit (Intel® NPU)
Audio Voice and Speech
Power Management
Power Delivery
Electrical Specifications
Thermal Management
System Clocks
Real Time Clock (RTC)
Memory
USB Type-C* Sub System
Universal Serial Bus (USB)
Intel® Volume Management Device (Intel® VMD) Technology
PCI Express* (PCIe*)
Serial ATA (SATA)
Graphics
Display
Processor Sideband Signals
General Purpose Input and Output
Interrupt Timer Subsystem (ITSS)
GPIO Serial Expander
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Gigabit Ethernet Controller
Connectivity Integrated (CNVi)
Controller Link
Integrated Sensor Hub (ISH)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Private Configuration Space Port ID
Testability and Monitoring
Miscellaneous Signals
Security Technologies
Intel® Converged Boot Guard and Intel® TXT
Crypto Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Prevention (Intel® SMEP)
Intel® Supervisor Mode Access Prevention (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
KeyLocker Technology
Intel® System Resources Defense and Intel® System Security Report
BIOS Guard
Intel® Platform Trust Technology
Security Firmware Engines
Audio Voice and Speech
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S / PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Power Management
System Power States, Advanced Configuration and Power Interface (ACPI)
Legacy Power Management Support
Functional Description
Processor IA Core Power Management
Processor Graphics Power Management
TCSS Power State
Power and Performance Technologies
Deprecated Technology
Power and Internal Signals
Power and Performance Technologies
Intel® Thread Director
Intel® Smart Cache Technology
P-core, E-core, and LP E-core Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Max Technology 3.0
Intel® Hyper-Threading Technology (Intel® HT Technology)
Intel® Turbo Boost Technology 2.0
Intel® Adaptive Boost Technology
Intel® System Agent Enhanced SpeedStep ® Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (Intel® DTT)
Cache Line Write Back (CLWB)
User Mode Wait Instructions
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THERMTRIP# Signal
Critical Temperature Detection
Software Controlled Clock Modulation (On-Demand Mode)
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
System Memory Controller Organization Mode
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
LPDDR5/x CMD/ADD Ascending and Descending
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
Processor IA Core C-State Rules
The following are general rules for all processor IA core C-states unless specified otherwise:
- A processor IA core C-State is determined by the lowest numerical thread state (such as Thread 0 requests C1E while Thread 1 requests C6 state, resulting in a processor IA core C1E state). Refer to the G, S, and C Interface State Combinations table.
- A processor IA core transitions to C0 state when:
- An interrupt occurs
- There is an access to the monitored address if the state was entered using an MWAIT/Timed MWAIT instruction
- The deadline corresponding to the Timed MWAIT instruction expires
- An interrupt directed toward a single thread wakes up only that thread.
- If any thread in a processor IA core is active (in C0 state), the core’s C-state will resolve to C0.
- Any interrupt coming into the processor package may wake any processor IA core.
- A system reset re-initializes all processor IA cores.
| Core C-State | C-State Request Instruction | Description |
|---|---|---|
| C0 | N/A | The normal operating state of a processor IA core where a code is being executed |
| C1 | MWAIT(C1) | AutoHalt - core execution stopped, autonomous clock gating (package in C0 state) |
| C1E | MWAIT(C1E) | Core C1 + lowest frequency and voltage operating point (package in C0 state) |
| C6-C10 | MWAIT(C6/C8/10) or IO read=P_LVL3//6/8 | Processor IA, flush their L1 instruction cache, the L1 data cache, and L2 cache to the LLC shared cache cores save their architectural state to an SRAM before reducing IA cores voltage, if possible may also be reduced to 0V. Core clocks are off. |
This feature is disabled by default. BIOS should enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register.