SMBus Target Interface
The Processor SMBus Target interface is accessed using the SMBus. The SMBus target logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting Protocol device. The target interface allows the Processor to decode cycles, and allows an external micro controller to perform specific actions.
Key features and capabilities include:
- Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify.
- Receive Target Address register: This is the address that the Processor decodes. A default value is provided so that the target interface can be used without the processor having to program this register.
- Receive Target Data register in the SMBus I/O space that includes the data written by the external micro controller.
- Registers that the external micro controller can read to get the state of the Processor .
- Status bits to indicate that the SMBus target logic caused an interrupt or SMI# Bit 0 of the target Status Register for the Host Notify command.
- Bit 16 of the SMI Status Register for all others.
The external micro controller should not attempt to access the Processor SMBus target logic until either: - 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR
- The PLTRST# de - asserts
If a controller leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more in the middle of a cycle, the Processor target logic's behavior is undefined. This is interpreted as an unexpected idle and should be avoided when performing management activities to the target logic.
Format of Target Write Cycle
The external controller performs Byte Write commands to the Processor SMBus Target I/F. The “Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 20:27) indicate the value that should be written to that register.
The table below has the values associated with the registers.
Target Write Registers
| Register | Function |
|---|
| 0 | Command Register. Refer to the table below for valid values written to this register. |
| 1–3 | Reserved |
| 4 | Data Message Byte 0 |
| 5 | Data Message Byte 1 |
| 6–FFh | Reserved |
| The external micro controller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. The Processor overwrites the old value with any new value received. A race condition is possible where the new value is being written to the register just at the time it is being read. The Processor will not attempt to cover this race condition (that is, unpredictable results in this case). |
Command Types
| Command Type | Description |
|---|
| 0 | Reserved |
| 1 | WAKE/SMI#. This command wakes the system if it is not already awake. If system is already awake, an SMI# is generated. |
| 2 | Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same effect as the Power button Override occurring. |
| 3 | HARD RESET WITHOUT CYCLING: This command causes a soft reset of the system (does not include cycling of the power supply). This is equivalent to a write to the CF9h register with Bits 2:1 set to 1, but Bit 3 set to 0. |
| 4 | HARD RESET SYSTEM. This command causes a hard reset of the system (including cycling of the power supply). This is equivalent to a write to the CF9h register with Bits 3:1 set to 1. |
| 5 | Disable the TCO Messages. This command will disable the Processor from sending Heartbeat and Event messages. Once this command has been executed, Heartbeat and Event message reporting can only be re - enabled by assertion and then de - assertion of the RSMRST# signal. |
| 6 | WD RELOAD: Reload watchdog timer. |
| 7 | Reserved |
| 8 | SMLINK_SLV_SMI. When the Processor detects this command type while in the S0 state, it sets the SMLINK_SLV_SMI_STS bit. This command should only be used if the system is in an S0 state. If the message is received during S4 and S5 states, the Processor acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set. It is possible that the system transitions out of the S0 state at the same time that the SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes to sleep. Once the system returns to S0, the SMI associated with this bit would then be generated. Software must be able to handle this scenario. |
| 9–FFh | Reserved. |
Format of Read Command
The external controller performs Byte Read commands to the Processor SMBus Target interface. The “Command” field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register.
Target Read Cycle Format
| Bit | Description | Driven By | Comment |
|---|
| 1 | Start | External Micro controller | |
| 2–8 | Target Address - 7 bits | External Micro controller | Must match value in Receive Target Address register |
| 9 | Write | External Micro controller | Always 0 |
| 10 | ACK | Processor | |
| 11–18 | Command code – 8 bits | External Micro controller | Indicates which register is being accessed. Refer to the Table below for a list of implemented registers. |
| 19 | ACK | Processor | |
| 20 | Repeated Start | External Micro controller | |
| 21–27 | Target Address - 7 bits | External Micro controller | Must match value in Receive Target Address register |
| 28 | Read | External Micro controller | Always 1 |
| 29 | ACK | Processor | |
| 30–37 | Data Byte | Processor | Value depends on register being accessed. Refer to the Table below for a list of implemented registers. |
| 38 | NOT ACK | External Micro controller | |
| 39 | Stop | External Micro controller | |
Data Values for Target Read Registers
| Register | Bits | Description |
|---|
| 0 | 7:0 | Reserved |
| 1 | 2:0 | System Power State 000 = S0 100 = S4 101 = S5 Others = Reserved |
| 7:3 | Reserved |
| 2 | 3:0 | Reserved |
| 7:4 | Reserved |
| 3 | 5:0 | Watchdog Timer current value The Watchdog Timer has 10 bits, but this field is only 6 bits. If the current value is greater than 3Fh, the Processor will always report 3Fh in this field. |
| 7:6 | Reserved |
| 4 | 0 | Intruder Detect. 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. |
| 1 | Reserved |
| 2 | Reserved |
| 3 | 1 = SECOND_TO_STS bit set. This bit will be set after the second Timeout (SECOND_TO_STS bit) of the Watchdog Timer occurs. |
| 6:4 | Reserved. Will always be 0, but software should ignore. |
| 7 | SMBALERT# Status. Reflects the value of the SMBALERT# pin (when the pin is configured to SMBALERT#). Valid only if SMBALERT_DISABLE = 0. Value always returns 1 if SMBALERT_DISABLE = 1. |
| 5 | 0 | Reserved |
| 1 | Battery Low Status. 1 if the BATLOW# pin a low. |
| 2 | SYS_PWROK Failure Status: This bit will be 1 if the SYSPWR_FLR bit in the GEN_PMCON_2 register is set. |
| 3 | Reserved |
| 4 | Reserved |
| 5 | POWER_OK_BAD: Indicates the failure core power well ramp during boot/resume. This bit will be active if the SLP_S3# pin is de - asserted and PLT_PWROK pin is not asserted. |
| 6 | Thermal Trip: This bit will shadow the state of processor Thermal Trip status bit (CTS). Events on signal will not create a event message |
| 7 | Reserved: Default value is “X” Software should not expect a consistent value when this bit is read through SMBUS/SMLink |
| 6 | 7:0 | Contents of the Message 1 register. |
| 7 | 7:0 | Contents of the Message 2 register. |
| 8 | 7:0 | Contents of the WDSTATUS register. |
| 9 | 7:0 | Seconds of the RTC |
| A | 7:0 | Minutes of the RTC |
| B | 7:0 | Hours of the RTC |
| C | 7:0 | “Day of Week” of the RTC |
| D | 7:0 | “Day of Month” of the RTC |
| E | 7:0 | Month of the RTC |
| F | 7:0 | Year of the RTC |
| 10h–FFh | 7:0 | Reserved |
- Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit—Address—Write bit sequence. When the Processor detects that the address matches the value in the Receive target Address register, it will assume that the protocol is always followed and ignore the Write bit (Bit 9) and signal an Acknowledge during bit 10. In other words, if a Start—Address—Read occurs (which is invalid for SMBus Read or Write protocol), and the address matches the Processor ’s Target Address, the Processor will still grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start—Address—Read sequence beginning at Bit 20. Once again, if the Address matches the Processor ’s Receive Target Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Target Read cycle.
Target Read of RTC Time Bytes
The Processor SMBus target interface allows external SMBus controller to read the internal RTC’s time byte registers.
The RTC time bytes are internally latched by the Processor’s hardware whenever RTC time is not changing and SMBus is idle. This ensures that the time byte delivered to the target read is always valid and it does not change when the read is still in progress on the bus. The RTC time will change whenever hardware update is in progress, or there is a software write to the RTC time bytes.
The Processor SMBus Target interface only supports Byte Read operation. The external SMBus controller will read the RTC time bytes one after another. It is the software’s responsibility to check and manage the possible time rollover when subsequent time bytes are read.
For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the external SMBus controller reads the hour as 11, then proceeds to read the minute, it is possible that the rollover happens between the reads and the minute is read as 0. This results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless it is certain that rollover will not occur, software is required to detect the possible time rollover by reading multiple times such that the read time bytes can be adjusted accordingly if needed.
Format of Host Notify Command
The Processor tracks and responds to the standard Host Notify command as specified in the System Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed to 0001000b. If the Processor already has data for a previously - received host notify command which has not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address byte of the protocol. This allows the host to communicate non - acceptance to the controller and retain the host notify address and data values for the previous cycle until host software completely services the interrupt.
Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary reads of the address and data registers. The table below shows the Host Notify format:
Host Notify Format
| Bit | Description | Driven By | Comment |
|---|
| 1 | Start | External Controller | |
| 8:2 | SMB Host Address – 7 bits | External Controller | Always 0001_000 |
| 9 | Write | External Controller | Always 0 |
| 10 | ACK (or NACK) | Processor | Processor NACKs if HOST_NOTIFY_STS is 1 |
| 17:11 | Device Address – 7 bits | External Controller | Indicates the address of the controller ; loaded into the Notify Device Address Register |
| 18 | Unused – Always 0 | External Controller | 7 - bit - only address; this bit is inserted to complete the byte |
| 19 | ACK | Processor | |
| 27:20 | Data Byte Low – 8 bits | External Controller | Loaded into the Notify Data Low Byte Register |
| 28 | ACK | Processor | |
| 36:29 | Data Byte High – 8 bits | External Controller | Loaded into the Notify Data High Byte Register |
| 37 | ACK | Processor | |
| 38 | Stop | External Controller | |
Format of Read Command
The external controller performs Byte Read commands to the Processor SMBus Target interface. The “Command” field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register.
Target Read Cycle Format
| Bit | Description | Driven By | Comment |
|---|
| 1 | Start | External Micro controller | |
| 2–8 | Target Address - 7 bits | External Micro controller | Must match value in Receive Target Address register |
| 9 | Write | External Micro controller | Always 0 |
| 10 | ACK | Processor | |
| 11–18 | Command code – 8 bits | External Micro controller | Indicates which register is being accessed. Refer to the Tale below for a list of implemented registers. |
| 19 | ACK | Processor | |
| 20 | Repeated Start | External Micro controller | |
| 21–27 | Target Address - 7 bits | External Micro controller | Must match value in Receive Target Address register |
| 28 | Read | External Micro controller | Always 1 |
| 29 | ACK | Processor | |
| 30–37 | Data Byte | Processor | Value depends on register being accessed. Refer to the Table below for a list of implemented registers. |
| 38 | NOT ACK | External Micro controller | |
| 39 | Stop | External Micro controller | |
Data Values for Target Read Registers
| Register | Bits | Description |
|---|
| 0 | 7:0 | Reserved for capabilities indication. Should always return 00h. Future chips may return another value to indicate different capabilities. |
| 1 | 2:0 | System Power State 000 = S0 100 = S4 101 = S5 Others = Reserved |
| 7:3 | Reserved |
| 2 | 3:0 | Reserved |
| 7:4 | Reserved |
| 3 | 5:0 | Watchdog Timer current value The Watchdog Timer has 10 bits, but this field is only 6 bits. If the current value is greater than 3Fh, the Processor will always report 3Fh in this field. |
| 7:6 | Reserved |
| 4 | 0 | Intruder Detect. 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. |
| 1 | Temperature Event. 1 = Temperature Event occurred. This bit will be set if the Processor ’s THRM# input signal is active. Else this bit will read “0.” |
| 2 | DOA Processor Status. This bit will be 1 to indicate that the processor is dead |
| 3 | 1 = SECOND_TO_STS bit set. This bit will be set after the second Timeout (SECOND_TO_STS bit) of the Watchdog Timer occurs. |
| 6:4 | Reserved. Will always be 0, but software should ignore. |
| 7 | SMBALERT# Status: Reflects the value of the GPIO11/SMBALERT# pin (when the pin is configured as SMBALERT#). Valid only if SMBALERT_DISABLE = 0. Value always return 1 if SMBALERT_DISABLE = 1. (high = 1, low = 0). |
| 5 | 0 | FWH bad bit: This bit will be 1 to indicate that the FWH read returned FFh, which indicates that it is probably blank. |
| 1 | Battery Low Status: 1 if the BATLOW# pin is a 0. |
| 2 | SYS_PWROK Failure Status: This bit will be 1 if the SYSPWR_FLR bit in the GEN_PMCON_2 register is set. |
| 3 | Reserved |
| 4 | Reserved |
| 5 | POWER_OK_BAD: Indicates the failure core power well ramp during boot/resume. This bit will be active if the PLT_PWROK pin is not asserted. |
| 6 | Thermal Trip: This bit will shadow the state of processor Thermal Trip status bit (CTS). Events on signal will not create a event message. |
| 7 | Reserved: Default value is “X” Software should not expect a consistent value when this bit is read through SMBUS/SMLink |
| 6 | 7:0 | Contents of the Message 1 register. |
| 7 | 7:0 | Contents of the Message 2 register. |
| 8 | 7:0 | Contents of the WDSTATUS register. |
| 9 | 7:0 | Seconds of the RTC |
| A | 7:0 | Minutes of the RTC |
| B | 7:0 | Hours of the RTC |
| C | 7:0 | “Day of Week” of the RTC |
| D | 7:0 | “Day of Month” of the RTC |
| E | 7:0 | Month of the RTC |
| F | 7:0 | Year of the RTC |
| 10h–FFh | 7:0 | Reserved |
Enables for SMBus Target Write and SMBus Host Events
| Event | INTREN (Host Control I/O Register, Offset 02h, Bit 0) | SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit 1) | Event |
|---|
| Target Write to Wake/SMI# Command | X | X | Wake generated when asleep. Target SMI# generated when awake (SMBUS_SMI_STS) |
| Target Write to SMLINK_SLAVE_SMI Command | X | X | Target SMI# generated when in the S0 state (SMBUS_SMI_STS) |
| Any combination of Host Status Register [4:1] asserted | 0 | X | None |
| 1 | 0 | Interrupt generated |
| 1 | 1 | Host SMI# generated |