Intel® Core™ Ultra Processor

Datasheet, Volume 1 of 2
Supporting Intel® Core™ Ultra Processor for U/H/U-Type4-series Platforms, formerly known as Meteor Lake

ID Date Version Classification
792044 05/09/2025 Public
Document Table of Contents

System Memory Timing Support

The IMC supports the following DDR Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

  • tCL = CAS Latency
  • tRCD = Activate Command to READ or WRITE Command delay
  • tRP = PRECHARGE Command Period
  • tRPb = per-bank PRECHARGE time
  • tRPab = all-bank PRECHARGE time
  • CWL = CAS Write Latency
  • Command Signal modes:
    • 2N indicates a new DDR5/LPDDR5/x command may be issued every 2 clocks
    • 1N indicates a new DDR5/LPDDR5/x command may be issued every clock

DDR5 System Memory Timing Support

DRAM Device

Transfer Rate (MT/s)

tCL (tCK)

tRCD (ns)

tRP (ns)

CWL (tCK)

CMD Mode

DDR5

4800

40

16.00

16.00

38

2N

DDR5

5600

46

16.00

16.00

44

2N

DDR5

6000

48

16.00

16.00

46

2N

DDR5

6400

52

16.00

16.00

50

2N

DDR5

6400

52

16.00

16.00

50

2N

LPDDR5/x System Memory Timing Support 

DRAM Device

Transfer Rate (MT/s)

tCL (tCK)

tRCD (ns)

tRPpb (ns)

tRPab (ns)

WL (tCK) Set B

LPDDR5

6400

17

18

18

21

16

LPDDR5x

7466

20

18

18

21

19