DDR0_​DQ[1:0][7:0]

DDR1_​DQ[1:0][7:0]

DDR2_​DQ[1:0][7:0]

DDR3_​DQ[1:0][7:0]

DDR4_​DQ[1:0][7:0]

DDR5_​DQ[1:0][7:0]

DDR6_​DQ[1:0][7:0]

DDR7_​DQ[1:0][7:0]

Data Buses: Data signals interface to the SDRAM data buses.

Example: DDR0_​DQ1[5] refers to DDR channel 0, Byte 1, Bit 5.

P/H/PX/HX/HX Refresh/U/U Refresh Processor Line

DDR0_​DQSP[1:0]

DDR1_​DQSP[1:0]

DDR2_​DQSP[1:0]

DDR3_​DQSP[1:0]

DDR4_​DQSP[1:0]

DDR5_​DQSP[1:0]

DDR6_​DQSP[1:0]

DDR7_​DQSP[1:0]

DDR0_​DQSN[1:0]

DDR1_​DQSN[1:0]

DDR2_​DQSN[1:0]

DDR3_​DQSN[1:0]

DDR4_​DQSN[1:0]

DDR5_​DQSN[1:0]

DDR6_​DQSN[1:0]

DDR7_​DQSN[1:0]

P/H/PX/HX/HX Refresh/U/U Refresh Processor Line

DDR0_​CLK_​N

DDR0_​CLK_​P

DDR1_​CLK_​N

DDR1_​CLK_​P

DDR2_​CLK_​N

DDR2_​CLK_​P

DDR3_​CLK_​N

DDR3_​CLK_​P

DDR4_​CLK_​N

DDR4_​CLK_​P

DDR5_​CLK_​N

DDR5_​CLK_​P

DDR6_​CLK_​N

DDR6_​CLK_​P

DDR7_​CLK_​N

DDR7_​CLK_​P

SDRAM Differential Clock:

Differential clocks signal pairs, pair per channel and package. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

P/H/PX/HX/HX Refresh/U/U Refresh Processor Line

DDR0_​CKE[1:0]

DDR1_​CKE[1:0]

DDR2_​CKE[1:0]

DDR3_​CKE[1:0]

DDR4_​CKE[1:0]

DDR5_​CKE[1:0]

DDR6_​CKE[1:0]

DDR7_​CKE[1:0]

Clock Enable: (1 per rank) These signals are used to:

• Initialize the SDRAMs during power-up.

• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of self-refresh during STR.

P/H/PX/HX/HX Refresh/U/U Refresh /U RefreshProcessor Line

DDR0_​CS[1:0]

DDR1_​CS[1:0]

DDR2_​CS[1:0]

DDR3_​CS[1:0]

DDR4_​CS[1:0]

DDR5_​CS[1:0]

DDR6_​CS[1:0]

DDR7_​CS[1:0]

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

The Chip select signal is Active High.

P/H/PX/HX/HX Refresh/U/U Refresh Processor Line

DDR0_​CA[5:0]

DDR1_​CA[5:0]

DDR2_​CA[5:0]

DDR3_​CA[5:0]

DDR4_​CA[5:0]

DDR5_​CA[5:0]

DDR6_​CA[5:0]

DDR7_​CA[5:0]

Command Address: These signals are used to provide the multiplexed command and address to the SDRAM.

P/H/PX/HX/HX Refresh/U /U RefreshProcessor Line

DDR0_​CA[6]

DDR1_​CA[6]

DDR2_​CA[6]

DDR3_​CA[6]

DDR4_​CA[6]

DDR5_​CA[6]

DDR6_​CA[6]

DDR7_​CA[6]

Command Address: These signals are used to provide the multiplexed command and address to the SDRAM.

P/H/PX/HX//HX RefreshU/U Refresh Processor Line

DDR[7:0]_​WCK_​N

Write Clocks: WCK_​N and WCK_​P are differential clocks used for WRITE data capture and READ data output.

P/H/PX/HX/HX Refresh/U/U Refresh Processor Line

DDR_​COMP

DDR_​RCOMP

System Memory Resistance Compensation

P/H/PX/HX/HX Refresh/U/U Refresh Processor Line

P/H/PX/HX/HX Refresh/U/U Refresh Processor Line