Processor Power Rails

13th Generation Intel® Core™ and Intel® Core™ 14th Generation Processors

Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S, H, P, HX, and U Processor Line Platforms, formerly known as Raptor Lake, Intel® Core™ 14th Generation Processor for S, HX, and U Processor Line Platform, formerly known as Raptor Lake Refresh and Intel® Xeon™ E 2400 Processor, formerly known As Raptor Lake–E

ID	Date	Version	Classification
743844	03/25/2024		Public

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Processor Power Rails Signals

Signal Name	Description	Dir.	Buffer Type	Link Type	Availability
VCCCORE	Processor IA Cores and Ring power rail	I	PWR	—	All Processor Lines
VCCGT	Processor Graphics power rail	I	PWR	—	All Processor Lines
VCCIN_AUX	Support internal FIVR’s, SA, PCIe, Display IO and other internal Blocks.	I	PWR	—	All Processor Lines
VCCIN_AUX_FLTR	Support internal FIVR’s, SA, PCIe, Display IO and other internal Blocks. this pin should be connected to decoupling for filter.	I	PWR	—	All Processor Lines
VCC1P05_PROC	Sustain and Sustain Gated Power Rail	I	PWR	—	All Processor Lines
VCC1P8_PROC	PCIE PHY Power 1.8V Rail	I	PWR	—	S/S Refresh/E Processor Line P Processor Line
VDD2	System Memory power rail	I	PWR	—	All Processor Lines
VDD2_EDGECAP	Internal power pin, this pin should be connected to a decoupling capacitor and ground	I	PWR	—	S/S Refresh/E Processor Line
VCCIN_AUX_EDGECAP	Internal power pin, this pin should be connected to a decoupling capacitor and ground	I	PWR	—	S/S Refresh/E Processor Line
VDD2_DDR5_SENSE	Isolated, low impedance DDR5 voltage sense pins.	N/A	PWR_ SENSE	—	S/S Refresh/E Processor Line
VCCGT_SENSE	Isolated, low impedance voltage sense pins. They can be used to sense or measure voltage near the silicon.	N/A	PWR_ SENSE	—	All Processor Lines
VCC_SENSE					All Processor Lines
VCCIN_AUX_SENSE / VCCINAUX_SENSE					All Processor Lines
VCC1P05_PROC_SENSE					S/S Refresh/E Processor Line
VCC1P05_PROC_OUT	VCC1P05_PROC_OUT is the power provider to the balls AR14 and AT12, so those three balls should be connected at board level.	O	PWR	—	P Processor Line U/U Refresh Processor Line
VCC_DISPIO	DDI PHY power rail (Shorted on package): Note:When no MIPI DSI interface is been used (only eDP), VCC_DISPIO should be shorted with VCC1P05_PROC_OUT, VCC_MIPILP can be left N.C. Note:When MIPI DSI interface is been used, VCC_MIPILP should be connected to 1.24v (on board VR), VCC_DISPIO can be left N.C.	I	PWR	—	P Processor Line U/U Refresh Processor Line
VCC_MIPILP		I	PWR	—	P Processor Line U/U Refresh Processor Line

Processor Ground Rails Signals

Signal Name	Description	Dir.	Buffer Type	Link Type	Availability
VSSGT_SENSE	Isolated, low impedance Ground sense pins. They can be used for the reference ground near the silicon.	N/A	GND_ SENSE	—	All Processor Lines
VSS_SENSE	All Processor Lines
VSSIN_AUX_SENSE / VSSINAUX_SENSE	All Processor Lines

Signal Name

Description

Dir.

Buffer Type

Link

Type

Availability

VSSGT_SENSE

Isolated, low impedance Ground sense pins. They can be used for the reference ground near the silicon.

N/A

GND_

SENSE

—

All Processor Lines

VSS_SENSE

All Processor Lines

VSSIN_AUX_SENSE / VSSINAUX_SENSE

All Processor Lines