| EKEY | Socket Electronic Key Used to distinguish between packages with different pins assignment. Connect this pin to the Enable signal of the first VR in sequence. Or as appropriate, to shut down complete power to SOC/platform when a wrong package is being used. | NA | NA | SE | S/S Refresh/E, HX/HX Refresh - Processor Line |
| SKTOCC# | Socket Occupied: Pulled down directly (0 Ohms) on the processor package to the ground. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present. | N/A | N/A | SE | P, H, HX/HX Refresh, PX, U/U Refresh - Processor Line |
| SKTOCC# | Socket Occupied: Pulled down directly (0 Ohms) on the processor package to the ground. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present. | O | O | SE | S/S Refresh/E - Processor Line |
| CFG[17:0] | Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. Intel recommends placing test points on the board for CFG pins. - CFG[1:0]: Reserved configuration lane
- CFG[5] S/S Refresh/E/HX/HX Refresh-Processor Line
PCI Express* Bifurcation - 0 = 2 x8 PCI Express*
- 1 = 1 x16 PCI Express* (default)
- CFG[5] H/P/PX/U/U Refresh-Processor Line
Reserved
- CFG[14]: S/S Refresh/E/HX/HX Refresh -Processor Line
PEG60 Lane Reversal: - 1 - (Default) Normal
- 0 - Reversed
- CFG[14]: H/P/PX/U/U Refresh-Processor Line
PEG60 Lane Reversal: - 1 - (Default) Normal
- 0 - Reversed
- CFG[15]: H/P/U/U Refresh-Processor Line
PEG62 Lane Reversal: - 1 - (Default) Normal
- 0 - Reversed
| I/O | GTL | SE | S/S Refresh/E-Processor Line P Processor Line H Processor Line U/U Refresh Processor Line HX/HX Refresh-Processor Line PX-Processor Line |
| VCC_CFG_PU_OUT | Power rail used by platform CFG straps for pull up resistors. | O | GTL | SE | S/S Refresh/E-Processor Line P Processor Line H Processor Line U/U Refresh Processor Line |
| EAR# | Stall reset sequence for early reset phases debug until deasserted: — 1 = (Default) Normal Operation; No stall. — 0 = Stall. | I | CMOS | SE | S/S Refresh/E-Processor Line P Processor Line H Processor Line U/U Refresh Processor Line |
| IST_TRIG | Impedance Spectrum Tool Trigger: trigger point to support debug of possible power issues. | O | GTL | SE | S/S Refresh/E-Processor Line P Processor Line H Processor Line U/U Refresh Processor Line |
| RESET# | Platform Reset pin driven by the PCH. | I | CMOS | SE | S/S Refresh/E-Processor Line P Processor Line H Processor Line U/U Refresh Processor Line |
| CPU_ID | A PLATFORM indication signal, for Compatibility option. | I | CMOS | SE | S/S Refresh/E-Processor Line P Processor Line H Processor Line U/U Refresh Processor Line |
| PROC_TRIGIN | Debug pin | I | CMOS | SE | S/S Refresh/E-Processor Line P Processor Line H Processor Line U/U Refresh Processor Line |
| PROC_TRIGOUT | O | CMOS | SE | S/S Refresh/E-Processor Line P Processor Line H Processor Line U/U Refresh Processor Line |