PCI Express* Support
The S/S Refresh/E processor PCI Express* has two interfaces:
- 16-lane (x16) port supporting PCIE to gen 5.0 or below that can also be configured as multiple ports at narrower widths.
- 4-lane (x4) port supporting PCIE gen 4.0 or below.
The HX/HX Refresh processor line PCI Express* has two interfaces:
- 16-lane (x16) port supporting PCIE to gen 5.0 or below that can also be configured as multiple ports at narrower widths.
- 4-lane (x4) port supporting PCIE gen 4.0 or below.
The H/ processor line PCI Express* has three interfaces:
- One 8-lane (x8) port supporting PCIE to gen 5.0 or below. This interface is available on certain SKU
- Two 4-lane (x4) port supporting PCIE gen 4.0 or below.
The PX processor line PCI Express* has two interfaces:
- One 8-lane (x8) port supporting PCIE to gen 4.0 or below. This interface is available on certain SKU
- One 4-lane (x4) port supporting PCIE gen 4.0 or below.
The P processor line PCI Express* has two interfaces:
- Two 4-lane (x4) port supporting PCIE gen 4.0 or below.
The U/U Refresh processor line PCI Express* has two interfaces:
- Two 4-lane (x4) port supporting PCIE gen 4.0 or below.
The processor supports the following:
PCIe Controller Feature | S/S Refresh/E/HX/HX Refresh - Processor Line | H/PX - Processor Line | P/U/U Refresh - Processor Line |
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PEG10 | PEG11 | PEG60 | PEG10 | PEG60 | PEG62 | PEG60 | PEG62 |
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PCIe Gen | Gen5 | Gen5 | Gen4 | Gen5 (H) Gen4 (PX) | Gen4 | Gen4 | Gen4 | Gen4 |
dGPU support | Yes | Yes | No | Yes | Yes | Yes | Yes [P], Yes [U]6 | Yes [P], Yes [U]6 |
SSD support | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Dynamic Width Change Support | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Dynamic Speed Change Support | No | No | No | No | No | No | No | No |
L1 PM Sub-States (L1.0, L1.1, L1.2) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
L0s Link State (RX/TX) | Yes | Yes | No | Yes | Yes | Yes | Yes | Yes |
S3/S4/S5 Sleep States (Sx) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Hierarchical configuration mechanism | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Traditional PCI style traffic (asynchronous snooped, PCI ordering) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Extended configuration space | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Enhanced Access Mechanism4 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
64-bit downstream address format2 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
64-bit upstream address format3 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Common Clock Mode | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Separate Reference Clock with Independent SSC (SRIS)4 | No | No | No | No | No | No | No | No |
Separate Reference Clock with No SSC (SRNS) | No | No | No | No | No | No | No | No |
Precision Time Measurement (PTM) | Yes | Yes | Yes1 | Yes | Yes1 | Yes1 | Yes1 | Yes1 |
Advanced Error Reporting (AER) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
End-to-End Lane Reversal | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Latency Tolerance Reporting (LTR) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
PCIe TX Half Swing | No | No | No | No | No | No | No | No |
PCIe TX Full Swing | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Run Time D3 (RTD3) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Modern Standby | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
MCTP VDM tunneling | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Message Signaled Interrupt (MSI) messages5 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Access Control Services (ACS) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Alternative Routing-ID Interpretation (ARI) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Port 80h Decode | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Receive Lane Polarity Inversion | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
PCIe Controller Root Port Hot-Plug | No | No | No | No | No | No | No | No |
Downstream Port Containment (DPC) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Enhanced Downstream Port Containment (eDPC) | No | No | No | No | No | No | No | No |
Virtual Channel (VC) | VC0 | VC0 | VC0/VC1 | VC0 | VC0/VC1 | VC0/VC1 | VC0/VC1 | VC0/VC1 |
NVMe Cycle Router | No | No | No | No | No | No | No | No |
Volume Management Device (Intel® VMD) Support | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Discrete Device Support (M.2 1px2, 1px4) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Hybrid Dual Port Module Support (M.2 2px2) | No | No | No | No | No | No | No | No |
Peer-2-Peer (P2P) Mem Write Transactions | No | No | Yes | No | No | Yes | Yes | Yes |
Peer-2-Peer (P2P) Mem Read Transactions | No | No | No | No | No | No | No | No |
Peer-2-Peer (P2P) MCTP Transactions | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
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Byte order ECN not supported - 4096 GB limit (Bits 63:43 always zeros)
- Processor responds to upstream read transactions to addresses above 4096 GB (addresses where any of Bits 63:43 are non-zero) with an Unsupported Request response. Upstream write transactions to addresses above 4096 GB will be dropped
- SRIS is enabled in PCH PCIe RP and not in CPU PCIe RP
- Only MSI is supported, MSI-X is not supported (no need for many vector)
- U/U Refresh dGPU is supported but not validated
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- Hierarchical PCI-compliant configuration mechanism for downstream devices.
- Traditional PCI style traffic (asynchronous snooped, PCI ordering).
- PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.
- PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory-mapped fashion.
- Automatic discovery, negotiation, and training of link out of reset.
- Multiple Virtual Channel for Gen 4 port only*.
- 64-bit downstream address format, but the processor never generates an address above 4096 GB (Bits 63:43 will always be zeros).
- 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 4096 GB (addresses where any of Bits 63:43 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 4096 GB will be dropped.
- Re-issues Configuration cycles that have been previously completed with the Configuration Retry status.
- PCI Express* reference clock is a 100-MHz differential clock.
- Power Management Event (PME) functions.
- Modern standby
- Dynamic width capability.
- Message Signaled Interrupt (MSI and MSI-X) messages.
- Lane reversal
- Advanced Error Reporting (AER)
- MCTP VDM tunneling.
- ACS - Access control services
- Precision Time Measurement (PTM) - This feature is supported on PEG60/62 with the exception of ECN for byte ordering of the PTM value not being supported. PEG10/11 do support ECN for byte ordering
The S/S Refresh/E/HX/HX Refresh processor supports the configurations shown in the following tables:
PCI Express* 16 - Lane Bifurcation and Lane Reversal Mapping
Bifurcation | Link Width | CFG Signals | Lanes |
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0:1:0 | 0:1:1 | CFG [6] | CFG [5] | CFG [2] | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
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PCIe controller | | PCIe 010 (PEG10) |
1x16 | x16 | N/A | 1 | 1 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
1x16 Reversed | x16 | N/A | 1 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCIe controller | | PCIe 010 (PEG10) | PCIe 011 (PEG11) |
2x8 | x8 | x8 | 1 | 0 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
PCIe controller | | PCIe 011 (PEG11) | PCIe 010 (PEG10) |
2x8 Reversed | x8 | x8 | 1 | 0 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- For CFG bus details, refer to Reset and Miscellaneous Signals.
- Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported.
- In case that more than one device is connected, the device with the highest lane count, should always be connected to the lower lanes, as follows:
- Connect lane 0 of 1st device to lane 0.
- Connect lane 0 of 2nd device to lane 8.
- For reversal lanes, for example: When using 1x8, the 8 lane device should use lanes 8:15, so lane 15 will be connected to lane 0 of the Device.
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S/S Refresh/E/HX/HX Refresh - Processor PCI Express* 4 - Lane Reversal Mapping
Bifurcation | Link Width | CFG Signals | Lanes |
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0:6:0 | CFG [14] | 0 | 1 | 2 | 3 |
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PCIe controller | PCIe 060 (PEG60) |
1x4 | x4 | 1 | 0 | 1 | 2 | 3 |
1x4 Reversed | x4 | 0 | 3 | 2 | 1 | 0 |
PCIe* Port60 is a single x4 port without bifurcation capabilities, thus bifurcation pin straps are not applicable. |
The H/PX processor lines supports the configurations shown in the following tables:
H/PX PCI Express* 8 - Lane Reversal Mapping
Bifurcation | Link Width | CFG Signals | Lanes |
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0:1:0 | 0:1:1 | CFG [6] | CFG [5] | CFG [2] | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
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PCIe controller | | PCIe 010 (PEG10) |
1x8 | x8 | N/A | 1 | 1 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1x8 Reversed | x8 | N/A | 1 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- For CFG bus details, refer to Reset and Miscellaneous Signals.
- Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported.
- For reversal lanes, for example: When using 1x4, the 4 lane device should use lanes 4:7, so lane 7 will be connected to lane 0 of the Device.
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The H/PX/P/U/U Refresh processor Lines supports the configurations shown in the following tables:
H/PX/P/U/U Refresh PCI Express* 4 - Lane Reversal Mapping
Bifurcation | Link Width | CFG Signals | Lanes |
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0:6:0 | 0:6:2 | CFG [14] | CFG [15] | 0 | 1 | 2 | 3 |
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PCIe Controller | PCIe 060 (PEG60) |
1x4 | x4 | NA | 1 | NA | 0 | 1 | 2 | 3 |
1x4 Reversed | x4 | NA | 0 | NA | 3 | 2 | 1 | 0 |
PCIe Controller | PCIe 062 (PEG62) |
1x4 | NA | x4 | NA | 1 | 0 | 1 | 2 | 3 |
1x4 Reversed | NA | x4 | NA | 0 | 3 | 2 | 1 | 0 |
PCI Express* Maximum Transfer Rates and Theoretical Bandwidth
PCI Express* Generation | Encoding | Maximum Transfer Rate [GT/s] | Theoretical Bandwidth [GB/s] |
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S/S Refresh/E/H/HX/HX Refresh /P/U/U Refresh x4 | S/S Refresh/E/H/HX/HX Refresh x8 | S/S Refresh/E/HX/HX Refresh x16 |
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Gen 1 | 8b/10b | 2.5 | 1.0 | 2.0 | 4.0 |
Gen 2 | 8b/10b | 5 | 2.0 | 4.0 | 8.0 |
Gen 3 | 128b/130b | 8 | 3.9 | 7.9 | 15.8 |
Gen 4 | 128b/130b | 16 | 7.9 | 15.8 | 31.5 |
Gen 5 | 128b/130b | 321 | 15.81 | 31.51 | 631 |
1. Transfer rate and max theoretical Bandwidth are not final and could be lowered. |
The above table summarizes the transfer rates and theoretical bandwidth of PCI Express* link.