13th Generation Intel® Core™, Intel® Core™ 14th Generation, Intel® Core™ Processor (Series 1) and (Series 2), Intel® Xeon™ E 2400 Processor and Intel® Xeon™ 6300 Processor
Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S, H, P, HX, and U Processor Line Platforms, formerly known as Raptor Lake.
Supporting Intel® Core™ 14th Generation Processor for S, HX formerly known As Raptor Lake Refresh.
Supporting Intel® Core™ Processor (Series 1) for U Processor Line Platform, formerly known As Raptor Lake refresh
Supporting Intel® Core™ Processor (Series 2) for H Processor Line Platform, formerly known As Raptor Lake Refresh.
Supporting Intel® Xeon® E 2400 Processor and Intel® Xeon® 6300 Processor, formerly known As Raptor Lake–E Refresh
PCI Express* Support
The S
- 16-lane (x16) port supporting PCIE to gen 5.0 or below that can also be configured as multiple ports at narrower widths.
- 4-lane (x4) port supporting PCIE gen 4.0 or below.
The HX
- 16-lane (x16) port supporting PCIE to gen 5.0 or below that can also be configured as multiple ports at narrower widths.
- 4-lane (x4) port supporting PCIE gen 4.0 or below.
The H/
- One 8-lane (x8) port supporting PCIE to gen 5.0 or below. This interface is available on certain SKU
- Two 4-lane (x4) port supporting PCIE gen 4.0 or below.
The PX processor line PCI Express* has two interfaces:
- One 8-lane (x8) port supporting PCIE to gen 4.0 or below. This interface is available on certain SKU
- One 4-lane (x4) port supporting PCIE gen 4.0 or below.
The P processor line PCI Express* has two interfaces:
The U
The processor supports the following:
- Hierarchical PCI-compliant configuration mechanism for downstream devices.
- Traditional PCI style traffic (asynchronous snooped, PCI ordering).
- PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.
- PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory-mapped fashion.
- Automatic discovery, negotiation, and training of link out of reset.
- Multiple Virtual Channel for Gen 4 port only*.
- 64-bit downstream address format, but the processor never generates an address above 4096 GB (Bits 63:43 will always be zeros).
- 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 4096 GB (addresses where any of Bits 63:43 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 4096 GB will be dropped.
- Re-issues Configuration cycles that have been previously completed with the Configuration Retry status.
- PCI Express* reference clock is a 100-MHz differential clock.
- Power Management Event (PME) functions.
- Modern standby
- Dynamic width capability.
- Message Signaled Interrupt (MSI and MSI-X) messages.
- Lane reversal
- Advanced Error Reporting (AER)
- MCTP VDM tunneling.
- ACS - Access control services
- Precision Time Measurement (PTM) - This feature is supported on PEG60/62 with the exception of ECN for byte ordering of the PTM value not being supported. PEG10/11 do support ECN for byte ordering
The S
| Bifurcation | Link Width | CFG Signals | Lanes | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0:1:0 | 0:1:1 | CFG [6] | CFG [5] | CFG [2] | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | ||
| PCIe controller | PCIe 010 (PEG10) | |||||||||||||||||||||
| 1x16 | x16 | N/A | 1 | 1 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | |
| 1x16 Reversed | x16 | N/A | 1 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PCIe controller | PCIe 010 (PEG10) | PCIe 011 (PEG11) | ||||||||||||||||||||
| 2x8 | x8 | x8 | 1 | 0 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
| PCIe controller | PCIe 011 (PEG11) | PCIe 010 (PEG10) | ||||||||||||||||||||
| 2x8 Reversed | x8 | x8 | 1 | 0 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ||||||||||||||||||||||
The H
| Bifurcation | Link Width | CFG Signals | Lanes | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0:1:0 | 0:1:1 | CFG [6] | CFG [5] | CFG [2] | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ||
| PCIe controller | PCIe 010 (PEG10) | |||||||||||||
| 1x8 | x8 | N/A | 1 | 1 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
| 1x8 Reversed | x8 | N/A | 1 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ||||||||||||||
The H
| Bifurcation | Link Width | CFG Signals | Lanes | |||||
|---|---|---|---|---|---|---|---|---|
| 0:6:0 | 0:6:2 | CFG [14] | CFG [15] | 0 | 1 | 2 | 3 | |
| PCIe Controller | PCIe 060 (PEG60) | |||||||
| 1x4 | x4 | NA | 1 | NA | 0 | 1 | 2 | 3 |
| 1x4 Reversed | x4 | NA | 0 | NA | 3 | 2 | 1 | 0 |
| PCIe Controller | PCIe 062 (PEG62) | |||||||
| 1x4 | NA | x4 | NA | 1 | 0 | 1 | 2 | 3 |
| 1x4 Reversed | NA | x4 | NA | 0 | 3 | 2 | 1 | 0 |
The above table summarizes the transfer rates and theoretical bandwidth of PCI Express* link.