PECI DC Characteristics

13th Generation Intel® Core™, Intel® Core™ 14th Generation, Intel® Core™ Processor (Series 1) and (Series 2), Intel® Xeon™ E 2400 Processor and Intel® Xeon™ 6300 Processor

Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S, H, P, HX, and U Processor Line Platforms, formerly known as Raptor Lake.
Supporting Intel® Core™ 14th Generation Processor for S, HX formerly known As Raptor Lake Refresh.
Supporting Intel® Core™ Processor (Series 1) for U Processor Line Platform, formerly known As Raptor Lake refresh
Supporting Intel® Core™ Processor (Series 2) for H Processor Line Platform, formerly known As Raptor Lake Refresh.
Supporting Intel® Xeon® E 2400 Processor and Intel® Xeon® 6300 Processor, formerly known As Raptor Lake–E Refresh

ID	Date	Version	Classification
743844	05/30/2025		Public

The PECI interface operates at a nominal voltage set by Vcc_{1p05_PROC}. The set of DC electrical specifications shown in the following table is used with devices normally operating from a Vcc_{1P05_PROC} interface supply.

Vcc_{1p05_PROC} nominal levels will vary between processor families. All PECI devices will operate at the Vcc_{1p05_PROC} level determined by the processor installed in the system.

PECI DC Electrical Limits

Symbol	Definition and Conditions	Minimum	Maximum	Units	Notes¹
R_up	Internal pull up resistance	15	45	Ω	3
V_in	Input Voltage Range	-0.15	Vcc1p05_PROC + 0.15	V	-
V_hysteresis	Hysteresis	0.1 * Vcc_{1p05_PROC}	—	V	-
V_IL	Input Voltage Low- Edge Threshold Voltage	0.275 * Vcc_{1p05_PROC}	0.525 * Vcc1p05_PROC	V	-
V_IH	Input Voltage High- Edge Threshold Voltage	0.550 * Vcc_{1p05_PROC}	0.725 *Vcc1p05_PROC	V	-
C_bus	Bus Capacitance per Node	—	10	pF	-
C_pad	Pad Capacitance	0.7	1.8	pF	-
Ileak000	leakage current @ 0 V	—	0.25	mA	-
Ileak100	leakage current @ Vcc_1p05	—	0.15	mA	-
Notes: Vcc_{1p05_PROC} supplies the PECI interface. PECI behavior does not affect Vcc_{1p05_PROC}minimum / maximum specifications. The leakage specification applies to powered devices on the PECI bus. The PECI buffer internal pull up resistance measured at 0.75* Vcc_{1p05_PROC}.

Input Device Hysteresis

The input buffers in both client and host models should use a Schmitt-triggered input design for improved noise immunity. Use the following figure as a guide for input buffer design.