31:9

0h

RO

Reserved

8

0x0

RW

(DDR4_​SKIP_​REFRESH_​EN)

DDR4 DRAM supports temperature controlled refresh and self refersh. The temperature controlled refresh is essentially DRAM controls to skip some refresh issued by the host when temperature is low enough. When this bit is set and MAD_​CHNL.DDR4=1, MC will enable DRAMs TC refresh mode aka skip refresh mode. Pcode uses MAD_​CHNL.DDR4 and PTM_​CTL.DDR4_​SKIP_​REFRESH_​EN to determine whether to support DDR thermal interrupt for refresh rate change. BIOS is responsible to configure this bit and is ZERO by default.

7

0x0

RW

(DISABLE_​DRAM_​TS)

When this bit is zero and MAD_​CHNL.LPDDR=1, pcode will use DDR MR4 for DIMM thermal status purposes.
Otherwise, pcode will ignore MR4 data and use the legacy CLTM/OLTM/EXTTS algorithms for computing DIMM thermal status.

6

0x0

RW

(PDWN_​CONFIG_​CTL)

This bit determined whether BIOS or pcode will control DDR powerdown modes and idle counter (via programming the PM_​PDWN_​config regs in iMC). When clear, pcode will manage the modes based on either core P-states or IA32_​ENERGY_​PERFORMANCE_​BIAS MSR value (when enabled). When set, BIOS is in control of DDR CKE mode and idle timer value, and pcode algorithm does not run.

5

0x0

RW/L

(LOCK_​PTM_​REGS_​PCU)

When set, several PCU registers related to DDR power/thermal management all become unwritable (writes will be silently ignored). List of registered locked by this bit is: DDR_​WARM_​THRESHOLD_​CH*, DDR_​HOT_​THRESHOLD_​CH*, DDR_​WARM_​BUDGET_​CH*, DDR_​HOT_​BUDGET_​CH*. Note that BIOS should complete its writes to all of the locked registers prior to setting this bit, since it can only be reset via uncore reset.

4

0x0

RW

(EXTTS_​ENABLE)

When clear (default), pcode ignores the EXTTS (external thermal status) indication which is obtained from the PCH (via PM_​SYNC). When set, the value from EXTTS is used only when it is hotter than the thermal status reported by OLTM/CLTM algorithm (or used all of the time if neither of those modes is enabled).

3:2

0x0

RW

(REFRESH_​2X_​MODE)

These bits are read by reset pcode and later broadcast (together with the thermal status) into the iMC cregs that control 2x refresh modes. When DRAM is hot, it accumulates bits errors more quickly. The iMC refresh mechanism is how those errors get prevented and corrected (using ECC). Thus in order to maintain an acceptable overall error rate, the refresh rate needs to increase with temperature. This is a very coarse grain mechanism for accomplishing that. A value of 00 means the iMC 2x refresh is disabled. A value of 01 means that the iMC will enable 2x refresh whenever thermal status is WARM or HOT. A value of 10 means the iMC will enable 2x refresh only when HOT. The value 11 is illegal, and will trigger an assertion in the iMC (BIOS should not do this). This field is ignored for LPDDR when DISABLE_​DRAM_​TS is zero, in which case refresh rates in the MC are controlled by MR4 coming directly from DIMMs.

1

0x0

RW

(CLTM_​ENABLE)

A value of 1 means CLTM (Closed Loop Thermal Management) pcode algorithm will be used to compute the memory thermal status (which will be written to the iMC). Note that OLTM and CLTM modes are mutex, so if both OLTM_​ENABLE and CLTM_​ENABLE are set, the OLTM_​ENABLE will be ignored and CTLM mode will be active. BIOS should enable CLTM whenever DIMM thermal sensor data is available and memory thermal management is desired.

0

0x0

RW

(OLTM_​ENABLE)

A value of 1 means OLTM (Open Loop Thermal Management) pcode algorithm will be used to compute the memory thermal status (which will be written to the iMC). Note that OLTM and CLTM modes are mutex, so if both OLTM_​ENABLE and CLTM_​ENABLE are set, the OLTM_​ENABLE will be ignored and CTLM mode will be active. BIOS should enable OLTM in case of thermal sensor data absence, but memory thermal management is desired. Obviously lack of real temperature data means this mode will be somewhat conservative, and may result in the iMC throttling more often than necessary. Thus for perf reasons CLTM is preferred on systems with available DIMM thermal sensor data.