12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767626 | 07/13/2023 | Public |
ACS Control Register (ACSCTLR) – Offset 226
ACS Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:7 | 0h | RO | Reserved |
6 | 0x0 | RO | ACS Direct Translated P2P Enable (TE) ACS Direct Translated P2P is not supported. |
5 | 0x0 | RO | ACS P2P Egress Control Enable (EE) ACS P2P Egress Control is not supported. |
4 | 0x0 | RW | ACS Upstream Forwarding Enable (UE) ACS Upstream Forwarding. |
3 | 0x0 | RW | ACS P2P Completion Redirect Enable (CE) Determines when the component redirects peer-to-peer Completions upstream - applicable only to Read Completions whose Relaxed Ordering Attribute is clear. |
2 | 0x0 | RW | ACS P2P Request Redirect Enable (RE) Determines when the component redirects peer-to-peer memory Requests targeting another peer port upstream. |
1 | 0x0 | RW | ACS Translation Blocking Enable (BE) When set, the component blocks all upstream Memory Requests whose Address Translation (AT) field is not set to the default value. |
0 | 0x0 | RW | ACS Source Validation Enable (VE) When set, the component validates the Bus Number from the Requester ID of upstream Requests against the secondary / subordinate Bus Numbers. |