Base of GTT Stolen Memory (BGSM_0_0_0_PCI) – Offset B4 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Base of GTT Stolen Memory (BGSM_0_0_0_PCI) – Offset B4

This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).

Bit Range	Default	Access	Field Name and Description
31:20	0x1	RW/L	(BGSM) This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 50 bits 7:6) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).
19:1	0h	RO	Reserved
0	0x0	RW/L	(LOCK) This bit will lock all writable settings in this register, including itself.

Bit Range

Default

Access

Field Name and Description

31:20

0x1

RW/L

(BGSM)

This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 50 bits 7:6) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).

19:1

Reserved

0x0

RW/L

(LOCK)

This bit will lock all writable settings in this register, including itself.

TSEG Memory Base (TSEGMB_0_0_0_PCI)

Base Data of Stolen Memory (BDSM_0_0_0_PCI) TSEG Memory Base (TSEGMB_0_0_0_PCI)