15:12

0h

RO

Reserved

11

0x0

RW/V2

Discard Timer SERR# Enable (DTSE)

Reserved per PCI-Express spec.
For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register is RW else it is RO. This register is only maintained for SW compatibility and has no functionality within the port.

10

0x0

RO

Discard Timer Status (DTS)

Reserved per PCI-Express spec.
For PCI Bus Emulation Mode compatibility, this register can remain RO as no secondary discard timer exists that will ever cause it to be set.

9

0x0

RW/V2

Secondary Discard Timer (SDT)

Reserved per Express spec.
For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register is RW else it is RO. This register is only maintained for SW compatibility and has no functionality within the port.

8

0x0

RW/V2

Primary Discard Timer (PDT)

Reserved per Express spec.
For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register is RW else it is RO. This register is only maintained for SW compatibility and has no functionality within the port.

7

0x0

RO

Fast Back to Back Enable (FBE)

Reserved per Express spec.

6

0x0

RW

Secondary Bus Reset (SBR)

Triggers a Hot Reset on the PCI-Express port.

5

0x0

RW/V2

Master Abort Mode (MAM)

Reserved per Express spec.
For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register is RW else it is RO. This register is only maintained for SW compatibility and has no functionality within the port.

4

0x0

RW

VGA 16-Bit Decode (V16)

When set, indicates that the I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled.
0: Execute 10-bit address decode on VGA I/O accesses.
1: Execute 16-bit address decode on VGA I/O accesses.

3

0x0

RW

VGA Enable (VE)

When set, the following ranges will be claimed off the backbone by the root port:
Memory ranges A0000h-BFFFFh
I/O ranges 3B0h - 3BBh and 3C0h - 3DFh, and all aliases of bits 15:10 in any combination of 1's

2

0x0

RW

ISA Enable (IE)

This bit only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64KB of PCI I/O space. If this bit is set, the root port will block any forwarding from the backbone to the device of I/O transactions addressing the last 768 bytes in each 1KB block (offsets 100h to 3FFh).

1

0x0

RW

SERR# Enable (SE)

When set, ERR_​COR, ERR_​NONFATAL, and ERR_​FATAL messages received are forwarded to the backbone. When cleared, they are not.

0

0x0

RW

Parity Error Response Enable (PERE)

When set, poisoned write TLPs and completions indicating poisoned TLPs will set the SSTS.DPD.