31:30

0x0

RW

Decoder Extended Bank Hashing (Decoder_​EBH)

Enable address decoder Extended bank hashing.
Bit 0: Enable XaB
Bit 1: Enable XbB

29:28

0x1

RW

BG0 Bit Options (BG0_​bit_​options)

depending on value, BG[0] will be replaced with C[5] or C[6].
DDR5:
0: CAS[5] = zoneaddr[8], BG[0] = zoneaddr[6]
1: CAS[5] = zoneaddr[6], BG[0] = zoneaddr[8]
2: CAS[6] = zoneaddr[6], BG[0] = zoneaddr[9]
3: Reserved
DDR4:
0: CAS[5] = zoneaddr[9], BG[0] = zoneaddr[6]
1: CAS[5] = zoneaddr[6], BG[0] = zoneaddr[9]
2: CAS[6] = zoneaddr[6], BG[0] = zoneaddr[10]
3: Reserved
for LPDDR5 BGMode only-
1: Swap BG[1]/CAS[6]
else: keep original BG[1]/CAS[6]
3: Reserved

27:26

0x0

RW

DIMM S Number of Ranks (DSNOR)

DIMM S number of ranks
0b: 1 Rank
1b: 2 Ranks

25:24

0x0

RW

DIMM S Width (DSW)

Width of DDR chips
0: X8 chips
1: X16 chips
2: X32 chips
3: Reserved

23

0h

RO

Reserved

22:16

0x0

RW

DIMM S Size (DIMM_​S_​SIZE)

Size of DIMM S in 0.5GB multiples.

15:13

0h

RO

Reserved

12

0x1

RW

DDR5 DIMM L capacity 8Gb (ddr5_​dl_​8Gb)

0: DDR5 DIMM L capacity is more than 8Gb
1: DDR5 DIMM L capacity is 8Gb

11

0x1

RW

DDR5 DIMM S capacity 8Gb (ddr5_​ds_​8Gb)

0: DDR5 DIMM S capacity is more than 8Gb
1: DDR5 DIMM S capacity is 8Gb

10:9

0x0

RW

DIMM L Number of Ranks (DLNOR)

0: 1 Rank
1: 2 Ranks
In ERM (enhanced rank mode):
2: 3 ranks
3: 4 ranks

8:7

0x0

RW

DIMM L Width (DLW)

DIMM L width of DDR chips
0: X8 chips
1: X16 chips
2: X32 chips
3: Reserved

6:0

0x0

RW

DIMM L Size (DIMM_​L_​SIZE)

Size of DIMM L in 0.5GB multiples