Channel 1 DIMM Characteristics (MAD_DIMM_CH1_0_0_0_MCHBAR) – Offset D810 - 1.3 - ID:767626 | 12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Channel 1 DIMM Characteristics (MAD_DIMM_CH1_0_0_0_MCHBAR) – Offset D810

This register defines the channel DIMM characteristics - number of DIMMs, number of ranks, size and type.

Bit Range	Default	Access	Field Name and Description
31:30	0x0	RW	Decoder Extended Bank Hashing (Decoder_EBH) Enable address decoder Extended bank hashing. Bit 0: Enable XaB Bit 1: Enable XbB
29:28	0x1	RW	BG0 Bit Options (BG0_bit_options) depending on value, BG[0] will be replaced with C[5] or C[6].DDR5: 0: CAS[5] = zoneaddr[8], BG[0] = zoneaddr[6] 1: CAS[5] = zoneaddr[6], BG[0] = zoneaddr[8] 2: CAS[6] = zoneaddr[6], BG[0] = zoneaddr[9] 3: Reserved DDR4: 0: CAS[5] = zoneaddr[9], BG[0] = zoneaddr[6] 1: CAS[5] = zoneaddr[6], BG[0] = zoneaddr[9] 2: CAS[6] = zoneaddr[6], BG[0] = zoneaddr[10] 3: Reserved
27:26	0x0	RW	DIMM S Number of Ranks (DSNOR) DIMM S number of ranks 0b: 1 Rank 1b: 2 Ranks
25:24	0x0	RW	DIMM S Width (DSW) Width of DDR chips 0: X8 chips 1: X16 chips 2: X32 chips 3: Reserved
23	0h	RO	Reserved
22:16	0x0	RW	DIMM S Size (DIMM_S_SIZE) Size of DIMM S in 0.5GB multiples.
15:13	0h	RO	Reserved
12	0x1	RW	DDR5 DIMM L capacity 8Gb (ddr5_dl_8Gb) 0: DDR5 DIMM L capacity is more than 8Gb 1: DDR5 DIMM L capacity is 8Gb
11	0x1	RW	DDR5 DIMM S capacity 8Gb (ddr5_ds_8Gb) 0: DDR5 DIMM S capacity is more than 8Gb 1: DDR5 DIMM S capacity is 8Gb
10:9	0x0	RW	DIMM L Number of Ranks (DLNOR) 0: 1 Rank 1: 2 Ranks In ERM (enhanced rank mode): 2: 3 ranks 3: 4 ranks
8:7	0x0	RW	DIMM L Width (DLW) DIMM L width of DDR chips 0: X8 chips 1: X16 chips 2: X32 chips 3: Reserved
6:0	0x0	RW	DIMM L Size (DIMM_L_SIZE) Size of DIMM L in 0.5GB multiples

Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR)

Channel 0 DIMM Characteristics (MAD_DIMM_CH0_0_0_0_MCHBAR) Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR)