12th Generation Intel® Core™ Processor Datasheet Volume 2 of 2

ID Date Version Classification
767626 07/13/2023 Public
Document Table of Contents
Introduction Processor Configuration Register Definitions and Address Ranges D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1) D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2) D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1) D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1) D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5) D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1) D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2) D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers D1:F0-1 PCI Express* Controller Registers D10:F0 Platform Monitoring Technology (PMT) Registers D14:F0 Volume Management Device D14:F0 Volume Management Device MEMBAR2 Registers D2:F0 Processor Graphics D4:F0 Dynamic Tuning Technology Registers D6:F0 PCI Express* Controller Registers D8:F0 Gauss Newton Algorithm Registers
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers Device Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Header Type (HTYPE) Secondary Status (SSTS) Subsystem Vendor ID (SVD) Capabilities List Pointer (CAPP) Bridge Control (BCTRL) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Root Control (RCTL) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Device Status 2 (DSTS2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Slot Capabilities 2 (SLCAP2) Slot Control 2 (SLCTL2) Slot Status 2 (SLSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Header Log (HL_DW1) Header Log (HL_DW2) Header Log (HL_DW3) Header Log (HL_DW4) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Lane 0 And Lane 1 Equalization Control (L01EC) Lane 2 And Lane 3 Equalization Control (L23EC) Lane 4 And Lane 5 Equalization Control (L45EC) Lane 6 And Lane 7 Equalization Control (L67EC) Lane 8 And Lane 9 Equalization Control (L89EC) Lane 10 And Lane 11 Equalization Control (L1011EC) Lane 12 And Lane 13 Equalization Control (L1213EC) Lane 14 And Lane 15 Equalization Control (L1415EC) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Capability Register (PL16CAP) Physical Layer 16.0 GT/s Control Register (PL16CTL) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 16.0 GT/s Extra Status Register (PL16ES) Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC) Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC) Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC) Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC) Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC) Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC) Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC) Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC) VNN Removal Control (VNNREMCTL) VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1) Device ID Override (DIDOVR) Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH) Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status (PL16MPCPS) Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS) Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS) Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS) Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS) Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS) Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS) Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS) Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS) Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS) Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS) Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS) Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS) Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS) Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS) Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS) Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers Version Register (VER_REG_0_0_0_VTDBAR) Capability Register (CAP_REG_0_0_0_VTDBAR) Extended Capability Register (ECAP_REG_0_0_0_VTDBAR) Global Command Register (GCMD_REG_0_0_0_VTDBAR) Global Status Register (GSTS_REG_0_0_0_VTDBAR) Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR) Context Command Register (CCMD_REG_0_0_0_VTDBAR) Fault Status Register (FSTS_REG_0_0_0_VTDBAR) Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR) Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR) Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR) Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR) Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR) Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR) Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR) Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR) Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR) Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR) Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR) Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR) Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR) Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR) Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR) Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR) Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR) Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR) Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR) Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR) Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR) Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR) Page Request Status Register (PRS_REG_0_0_0_VTDBAR) Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR) Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR) Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR) Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR) MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR) MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR) Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR) Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR) Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR) Invalidate Address Register (IVA_REG_0_0_0_VTDBAR) IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5) IMR0BASE (IMR0BASE_0_0_0_MCHBAR_IMPH) IMR0MASK (IMR0MASK_0_0_0_MCHBAR_IMPH) IMR1BASE (IMR1BASE_0_0_0_MCHBAR_IMPH) IMR1MASK (IMR1MASK_0_0_0_MCHBAR_IMPH) IMR2BASE (IMR2BASE_0_0_0_MCHBAR_IMPH) IMR2MASK (IMR2MASK_0_0_0_MCHBAR_IMPH) IMR3BASE (IMR3BASE_0_0_0_MCHBAR_IMPH) IMR3MASK (IMR3MASK_0_0_0_MCHBAR_IMPH) IMR4BASE (IMR4BASE_0_0_0_MCHBAR_IMPH) IMR4MASK (IMR4MASK_0_0_0_MCHBAR_IMPH) IMR5BASE (IMR5BASE_0_0_0_MCHBAR_IMPH) IMR5MASK (IMR5MASK_0_0_0_MCHBAR_IMPH) IMR6BASE (IMR6BASE_0_0_0_MCHBAR_IMPH) IMR6MASK (IMR6MASK_0_0_0_MCHBAR_IMPH) IMR7BASE (IMR7BASE_0_0_0_MCHBAR_IMPH) IMR7MASK (IMR7MASK_0_0_0_MCHBAR_IMPH) IMR8BASE (IMR8BASE_0_0_0_MCHBAR_IMPH) IMR8MASK (IMR8MASK_0_0_0_MCHBAR_IMPH) IMR9BASE (IMR9BASE_0_0_0_MCHBAR_IMPH) IMR9MASK (IMR9MASK_0_0_0_MCHBAR_IMPH) IMR10BASE (IMR10BASE_0_0_0_MCHBAR_IMPH) IMR10MASK (IMR10MASK_0_0_0_MCHBAR_IMPH) IMR11BASE (IMR11BASE_0_0_0_MCHBAR_IMPH) IMR11MASK (IMR11MASK_0_0_0_MCHBAR_IMPH) IMR12BASE (IMR12BASE_0_0_0_MCHBAR_IMPH) IMR12MASK (IMR12MASK_0_0_0_MCHBAR_IMPH) IMR13BASE (IMR13BASE_0_0_0_MCHBAR_IMPH) IMR13MASK (IMR13MASK_0_0_0_MCHBAR_IMPH) IMR14BASE (IMR14BASE_0_0_0_MCHBAR_IMPH) IMR14MASK (IMR14MASK_0_0_0_MCHBAR_IMPH) IMR15BASE (IMR15BASE_0_0_0_MCHBAR_IMPH) IMR15MASK (IMR15MASK_0_0_0_MCHBAR_IMPH) IMR16BASE (IMR16BASE_0_0_0_MCHBAR_IMPH) IMR16MASK (IMR16MASK_0_0_0_MCHBAR_IMPH) IMR17BASE (IMR17BASE_0_0_0_MCHBAR_IMPH) IMR17MASK (IMR17MASK_0_0_0_MCHBAR_IMPH) IMR18BASE (IMR18BASE_0_0_0_MCHBAR_IMPH) IMR18MASK (IMR18MASK_0_0_0_MCHBAR_IMPH)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1) BIOS POST Code (BIOS_POST_CODE_0_0_0_MCHBAR_PCU) (DDR_PTM_CTL_0_0_0_MCHBAR_PCU) Package RAPL Performance Status (PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR_PCU) Primary Plane Turbo Policy (PRIP_TURBO_PLCY_0_0_0_MCHBAR_PCU) Secondary Plane Turbo Policy (SECP_TURBO_PLCY_0_0_0_MCHBAR_PCU) Primary Plane Energy Status (PRIP_NRG_STTS_0_0_0_MCHBAR_PCU) Secondary Plane Energy Status (SECP_NRG_STTS_0_0_0_MCHBAR_PCU) Package Power SKU Unit (PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR_PCU) Package Energy Status (PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR_PCU) Primary Plane 0 Temperature (PP0_TEMPERATURE_0_0_0_MCHBAR_PCU) RP-State Limits (RP_STATE_LIMITS_0_0_0_MCHBAR_PCU) Package Power Limit (PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU) Device Idle Duration Override (DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU) FIVR FFFC EMI Control (FFFC_EMI_CONTROL_0_0_0_MCHBAR_PCU) FIVR FFFC RFI Control (FFFC_RFI_CONTROL_0_0_0_MCHBAR_PCU) FIVR FFFC RFI Control 2 (FFFC_RFI_CONTROL2_0_0_0_MCHBAR_PCU) BIOS Mailbox Data (BIOS_Mailbox_Data_0_0_0_MCHBAR_PCU) BIOS Mailbox Interface (BIOS_Mailbox_Interface_0_0_0_MCHBAR_PCU) BIOS Reset Complete (BIOS_RESET_CPL_0_0_0_MCHBAR_PCU) Memory Controller BIOS Request (MC_BIOS_REQ_0_0_0_MCHBAR_PCU) Memory Controller BIOS Data (MC_BIOS_DATA_0_0_0_MCHBAR_PCU) System Agent Power Management Control (SAPMCTL_0_0_0_MCHBAR_PCU) Configurable TDP Nominal (CONFIG_TDP_NOMINAL_0_0_0_MCHBAR_PCU) Configurable TDP Level 1 (CONFIG_TDP_LEVEL1_0_0_0_MCHBAR_PCU) Configurable TDP Level 2 (CONFIG_TDP_LEVEL2_0_0_0_MCHBAR_PCU) Configurable TDP Control (CONFIG_TDP_CONTROL_0_0_0_MCHBAR_PCU) Turbo Activation Ratio (TURBO_ACTIVATION_RATIO_0_0_0_MCHBAR_PCU) Overclocking Status (OC_STATUS_0_0_0_MCHBAR_PCU) Base Clock (BCLK) Frequency (BCLK_FREQ_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers Egress Port Virtual Channel Capabilities (EPVCECH) Egress Port VC Capability Register 1 (EPPVCCAP1) Egress Port VC Capability Register 2 (EPPVCCAP2) Egress Port VC Control (EPPVCCTL) Egress Port Virtual Channel 0 Resource Capability (EPVC0RCAP) Egress Port Virtual Channel 0 Resource Control (EPVC0RCTL) Egress Port Virtual Channel 0 Resource Status (EPVC0RSTS) Egress Port Virtual Channel 1 Resource Capability (EPVC1RCAP) Egress Port Virtual Channel 1 Resource Control (EPVC1RCTL) Egress Port Virtual Channel 1 Resource Status (EPVC1RSTS) Egress Port Capablity Declaration (EPRCLDECH) Egress Port Element Declaration Capability (EPESD) Egress Port Link Element Declaration 1 (EPLE1D) Egress Port Link Another Root Complex Declaration 1 (EPLE1A) Egress Port Second Link Declaration 1 (EPULE1A) Egress Port Link Element Declaration 2 (EPLE2D) Egress Port Link Another Root Complex Declaration 2 (EPLE2A) Egress Port Second Link Declaration 2 (EPULE2A) Egress Port Link Element Declaration 3 (EPLE3D) Egress Port Link Another Root Complex Declaration 3 (EPLE3A) Egress Port Second Link Declaration 3 (EPULE3A) Egress Port Link Element Declaration 4 (EPLE4D) Egress Port Link Another Root Complex Declaration 4 (EPLE4A) Egress Port Second Link Declaration 4 (EPULE4A) Egress Port Link Element Declaration 5 (EPLE5D) Egress Port Link Another Root Complex Declaration 5 (EPLE5A) Egress Port Second Link Declaration 5 (EPULE5A) Miscellaneous Port Configuration PXPEPBAR (MPCP)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers Version Register (VER_REG_0_0_0_VTDBAR) Capability Register (CAP_REG_0_0_0_VTDBAR) Extended Capability Register (ECAP_REG_0_0_0_VTDBAR) Global Command Register (GCMD_REG_0_0_0_VTDBAR) Global Status Register (GSTS_REG_0_0_0_VTDBAR) Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR) Context Command Register (CCMD_REG_0_0_0_VTDBAR) Fault Status Register (FSTS_REG_0_0_0_VTDBAR) Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR) Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR) Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR) Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR) Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR) Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR) Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR) Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR) Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR) Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR) Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR) Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR) Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR) Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR) Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR) Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR) Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR) Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR) Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR) Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR) Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR) Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR) Page Request Status Register (PRS_REG_0_0_0_VTDBAR) Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR) Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR) Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR) Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR) MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR) MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR) Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR) Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR) Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR) Invalidate Address Register (IVA_REG_0_0_0_VTDBAR) IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR)
D1:F0-1 PCI Express* Controller Registers Device ID and Vendor ID (ID) Device Command (CMD) Primary Status (PSTS) Revision ID and Class Code (RID_CC) Cache Line Size (CLS) Primary Latency Timer (PLT) Header Type (HTYPE) Base Address Register 0 (BAR0) Base Address Register 1 (BAR1) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities Pointer (CAPP) Interrupt Information Byte 0 (INTRB0) Interrupt Information Byte 1 (INTRB1) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Capabilities (ROOTCAP) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Device Status 2 (DSTS2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Slot Capabilities 2 (SLCAP2) Slot Control 2 (SLCTL2) Slot Status 2 (SLSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Upper Address (MUA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Header Log (HL_DW1) Header Log (HL_DW2) Header Log (HL_DW3) Header Log (HL_DW4) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) TLP Prefix Log 1 (TLPPL1) TLP Prefix Log 2 (TLPPL2) TLP Prefix Log 3 (TLPPL3) TLP Prefix Log 4 (TLPPL4) PTM Extended Capability Header (PTMECH) PTM Capability (PTMCAPR) PTM Control (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability (ACSCAPR) ACS Control (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability (DPCCAPR) DPC Control (DPCCTLR) DPC Status (DPCSR) DPC Error Source ID (DPCESIDR) RP PIO Status (RPPIOSR) RP PIO Mask (RPPIOMR) RP PIO Severity (RPPIOVR) RP PIO SysError (RPPIOSER) RP PIO Exception (RPPIOER) RP PIO Header Log DW1 (RPPIOHLR_DW1) RP PIO Header Log DW2 (RPPIOHLR_DW2) RP PIO Header Log DW3 (RPPIOHLR_DW3) RP PIO Header Log DW4 (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Lane 0 And Lane 1 Equalization Control (L01EC) Lane 2 And Lane 3 Equalization Control (L23EC) Lane 4 And Lane 5 Equalization Control (L45EC) Lane 6 And Lane 7 Equalization Control (L67EC) Lane 8 And Lane 9 Equalization Control (L89EC) Lane 10 And Lane 11 Equalization Control (L1011EC) Lane 12 And Lane 13 Equalization Control (L1213EC) Lane 14 And Lane 15 Equalization Control (L1415EC) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities (DLFCAP) Data Link Feature Status (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Capability (PL16CAP) Physical Layer 16.0 GT/s Control (PL16CTL) Physical Layer 16.0 GT/s Status (PL16S) Physical Layer 16.0 GT/s Local Data Parity Mismatch Status (PL16LDPMS) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status (PL16SRDPMS) Physical Layer 16.0 GT/s Extra Status (PL16ES) Physical Layer 16.0 GT/s Lane 01 Equalization Control (PL16L01EC) Physical Layer 16.0 GT/s Lane 23 Equalization Control (PL16L23EC) Physical Layer 16.0 GT/s Lane 45 Equalization Control (PL16L45EC) Physical Layer 16.0 GT/s Lane 67 Equalization Control (PL16L67EC) Physical Layer 16.0 GT/s Lane 89 Equalization Control (PL16L89EC) Physical Layer 16.0 GT/s Lane 1011 Equalization Control (PL16L1011EC) Physical Layer 16.0 GT/s Lane 1213 Equalization Control (PL16L1213EC) Physical Layer 16.0 GT/s Lane 1415 Equalization Control (PL16L1415EC) Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) Physical Layer 32.0 GT/s Capability (G5CAP) Physical Layer 32.0 GT/s Control (G5CTL) Physical Layer 32.0 GT/s Status (G5STS) Receiver Modified TS Data 1 (RCVDMODTSDATA1) Receiver Modified TS Data 2 (RCVDMODTSDATA2) Transmitted Modified TS Data 1 (TRNSMODTSDATA1) Transmitted Modified TS Data 2 (TRNSMODTSDATA2) 32.0 GT/s Lane 0123 Equalization Control (G5LANEEQCTL_0) 32.0 GT/s Lane 4567 Equalization Control (G5LANEEQCTL_4) 32.0 GT/s Lane 891011 Equalization Control (G5LANEEQCTL_8) 32.0 GT/s Lane 12131415 Equalization Control (G5LANEEQCTL_12) Alternate Protocol Extended Capability Header (APEC) Alternate Protocol Capabilities (APCAPR) Alternate Protocol Control (APCTRLR) Alternate Protocol Data 1 (APD1R) Alternate Protocol Data 2 (APD2R) Alternate Protocol Selective Enable Mask (APSEMR) Multicast Extended Capability Header (MCECH) Multicast Extended Capability (MCAPR) Multicast Control (MCCTLR) Multicast Base Address Register 1 (MCBADRR1) Multicast Base Address Register 2 (MCBADRR2) Multicast Receive (MCRR) Multicast Block All (MCBAR) Multicast Block Untranslated (MCBUR) Multicast Overlay BAR 1 (MCOB1) Multicast Overlay BAR 2 (MCOB2) VNN Removal Control (VNNREMCTL) VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1) Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH) Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 0 & 1 (PL16MPCPSB01) Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23) Physical Layer 16.0 GT/s Lane0 Margin Control and Status (PL16L0MCS) Physical Layer 16.0 GT/s Lane1 Margin Control and Status (PL16L1MCS) Physical Layer 16.0 GT/s Lane2 Margin Control and Status (PL16L2MCS) Physical Layer 16.0 GT/s Lane3 Margin Control and Status (PL16L3MCS) Physical Layer 16.0 GT/s Lane4 Margin Control and Status (PL16L4MCS) Physical Layer 16.0 GT/s Lane5 Margin Control and Status (PL16L5MCS) Physical Layer 16.0 GT/s Lane6 Margin Control and Status (PL16L6MCS) Physical Layer 16.0 GT/s Lane7 Margin Control and Status (PL16L7MCS) Physical Layer 16.0 GT/s Lane8 Margin Control and Status (PL16L8MCS) Physical Layer 16.0 GT/s Lane9 Margin Control and Status (PL16L9MCS) Physical Layer 16.0 GT/s Lane10 Margin Control and Status (PL16L10MCS) Physical Layer 16.0 GT/s Lane11 Margin Control and Status (PL16L11MCS) Physical Layer 16.0 GT/s Lane12 Margin Control and Status (PL16L12MCS) Physical Layer 16.0 GT/s Lane13 Margin Control and Status (PL16L13MCS) Physical Layer 16.0 GT/s Lane14 Margin Control and Status (PL16L14MCS) Physical Layer 16.0 GT/s Lane15 Margin Control and Status (PL16L15MCS)
D2:F0 Processor Graphics Vendor ID (VID2_0_2_0_PCI) Device ID (DID2_0_2_0_PCI) PCI Command (PCICMD_0_2_0_PCI) PCI Status (PCISTS2_0_2_0_PCI) Revision ID and Class Code (RID2_CC_0_2_0_PCI) Cache Line Size (CLS_0_2_0_PCI) Master Latency Timer (MLT2_0_2_0_PCI) Header Type (HDR2_0_2_0_PCI) Built In Self Test (BIST_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI) Graphics Memory Range Address (GMADR0_0_2_0_PCI) Graphics Memory Range Address (GMADR1_0_2_0_PCI) I/O Base Address (IOBAR_0_2_0_PCI) Subsystem Vendor ID (SVID2_0_2_0_PCI) Subsystem ID (SID2_0_2_0_PCI) Video BIOS ROM Base Address (ROMADR_0_2_0_PCI) Capabilities Pointer (CAPPOINT_0_2_0_PCI) Interrupt Line (INTRLINE_0_2_0_PCI) Interrupt Pin (INTRPIN_0_2_0_PCI) Minimum Grant (MINGNT_0_2_0_PCI) Maximum Latency (MAXLAT_0_2_0_PCI) Capability Identifier (CAPID0_0_2_0_PCI) Capabilities Control (CAPCTRL0_0_2_0_PCI) Capabilities A (CAPID0_A_0_2_0_PCI) Capabilities B (CAPID0_B_0_2_0_PCI) PCI Mirror of GMCH Graphics Control (MGGC0_0_2_0_PCI) Mirror of Device Enable (DEVEN0_0_2_0_PCI) Device 2 Control (DEV2CTL_0_2_0_PCI) Multi Size Aperture Control (MSAC_0_2_0_PCI) Push Aperture (PUSHAP_0_2_0_PCI) VTd Status (VTD_STATUS_0_2_0_PCI) PCI Express Capability Header (PCIECAPHDR_0_2_0_PCI) PCI Express Capability (PCIECAP_0_2_0_PCI) Device Capabilities (DEVICECAP_0_2_0_PCI) PCI Express Device Control (DEVICECTL_0_2_0_PCI) PCI Express Capability Structure (DEVICESTS_0_2_0_PCI) Message Signaled Interrupts Capability ID (MSI_CAPID_0_2_0_PCI) Message Control (MC_0_2_0_PCI) Message Address (MA_0_2_0_PCI) Message Data (MD_0_2_0_PCI) MSI Mask Bits (MSI_MASK_0_2_0_PCI) MSI Pending Bits (MSI_PEND_0_2_0_PCI) Mirror of Base Data of Stolen Memory (BDSM0_0_2_0_PCI) Mirror of Base Data of Stolen Memory (BDSM1_0_2_0_PCI) Graphics VTD Base Address LSB (GFXVTDBAR_LSB_0_2_0_PCI) GFX_VTDBAR_MSB (GFXVTDBAR_MSB_0_2_0_PCI) Power Management Capabilities ID (PMCAPID_0_2_0_PCI) Power Management Capabilities (PMCAP_0_2_0_PCI) Power Management Control and Status (PMCS_0_2_0_PCI) Software SMI (SWSMI_0_2_0_PCI) Graphics System Event (GSE_0_2_0_PCI) Software SCI (SWSCI_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC1_0_2_0_PCI) Stepping Revision ID (SRID_0_2_0_PCI) ASL Storage (ASLS_0_2_0_PCI) PASID Extended Capability Header (PASID_EXTCAP_0_2_0_PCI) PASID Capability (PASID_CAP_0_2_0_PCI) PASID Control (PASID_CTRL_0_2_0_PCI) ATS Extended Capability Header (ATS_EXTCAP_0_2_0_PCI) ATS Capability (ATS_CAP_0_2_0_PCI) ATS Control (ATS_CTRL_0_2_0_PCI) Page Request Extended Capability Header (PR_EXTCAP_0_2_0_PCI) Page Request Control (PR_CTRL_0_2_0_PCI) Page Request Status (PR_STATUS_0_2_0_PCI) Outstanding Page Request Capacity (OPRC_0_2_0_PCI) Outstanding Page Request Allocation (OPRA_0_2_0_PCI) SRIOV Extended Capability Header (SRIOV_ECAPHDR_0_2_0_PCI) SRIOV Capabilities (SRIOV_CAP_0_2_0_PCI) SRIOV Status (SRIOV_STS_0_2_0_PCI) SRIOV Initial VFs (SRIOV_INITVFS_0_2_0_PCI) SRIOV Total VFs (SRIOV_TOTVFS_0_2_0_PCI) First VF Offset (FIRST_VF_OFFSET_0_2_0_PCI) VF Stride (VF_STRIDE_0_2_0_PCI) VF Device ID (VF_DEVICEID_0_2_0_PCI) Supported Page Sizes (SUPPORTED_PAGE_SIZES_0_2_0_PCI) System Page Sizes (SYSTEM_PAGE_SIZES_0_2_0_PCI) VF BAR0 Lower DWORD (VF_BAR0_LDW_0_2_0_PCI) VF BAR0 Upper DWORD (VF_BAR0_UDW_0_2_0_PCI) VF BAR1 Lower DWORD (VF_BAR1_LDW_0_2_0_PCI) VF BAR1 Upper DWORD (VF_BAR1_UDW_0_2_0_PCI) VF Migration State Array Offset (VF_MIGST_OFFSET_0_2_0_PCI)
D6:F0 PCI Express* Controller Registers Device ID and Vendor ID (ID) Device Command (CMD) Primary Status (PSTS) Revision ID and Class Code (RID_CC) Cache Line Size (CLS) Primary Latency Timer (PLT) Header Type (HTYPE) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information (INTR) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Capabilities Pointer (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Device Status 2 (DSTS2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Slot Capabilities 2 (SLCAP2) Slot Control 2 (SLCTL2) Slot Status 2 (SLSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Channel Configuration (CCFG) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Header Log (HL_DW1) Header Log (HL_DW2) Header Log (HL_DW3) Header Log (HL_DW4) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Lane 0 And Lane 1 Equalization Control (L01EC) Lane 2 And Lane 3 Equalization Control (L23EC) Lane 4 And Lane 5 Equalization Control (L45EC) Lane 6 And Lane 7 Equalization Control (L67EC) Lane 8 And Lane 9 Equalization Control (L89EC) Lane 10 And Lane 11 Equalization Control (L1011EC) Lane 12 And Lane 13 Equalization Control (L1213EC) Lane 14 And Lane 15 Equalization Control (L1415EC) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Capability Register (PL16CAP) Physical Layer 16.0 GT/s Control Register (PL16CTL) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 16.0 GT/s Extra Status Register (PL16ES) Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC) Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC) Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC) Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC) Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC) Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC) Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC) Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC) VNN Removal Control (VNNREMCTL) VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1) Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH) Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status (PL16MPCPS) Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS) Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS) Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS) Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS) Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS) Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS) Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS) Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS) Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS) Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS) Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS) Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS) Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS) Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS) Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS) Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)

Channel Configuration (CCFG) – Offset D0

Channel Configuration

Bit Range

Default

Access

Field Name and Description

31

0x0

RW/L

Config Receive Enabled (CRE)

When set, enables receiving upstream configuration cycles which are normally not allowed. These may be peer cycles or sent to DMI depending upon the result of peer decode. When cleared, upstream configuration cycles will be completed with Unsupported Request completion status.
This register is Read-Only if LPCR.SRL field is set.

30

0x0

RW/L

I/O Receive Enabled (IORE)

When set, enables receiving upstream IO cycles which are normally not allowed. These may be peer cycles or sent to DMI depending upon the result of peer decode. When cleared, upstream I/O cycles will be completed with Unsupported Request completion status.
This register is Read-Only if LPCR.SRL field is set.

29

0h

RO

Reserved

28

0x0

RW

Upstream Fabric Decode Mode (UFDM)

When is cleared, DMI would send all Upstream transactions using Implicit Decode except for NVMe peer usages which would use Fabric Decode.
When is set, DMI will force all Upstream transactions to use Fabric Decode.

27

0x1

RW

Upstream Atomic Request Peer Disable (UARPD)

When set, Upstream Atomic Request will be forwarded to fabric using implicit decode, bypassing the peer decode phase. This results in shorter Atomic latency to memory.
When clear, Upstream Atomic Request will be forwarded to fabric using fabric decode, unless specifically called out otherwise.
This bit can only be set if the platform does not support peer-to-peer atomic request.

26

0x1

RW

Upstream Memory Read Peer Disable (UMRPD)

When set, upstream memory reads will be forwarded to fabric using implicit decode, bypassing the peer decode phase. This results in shorter memory read latency to memory.
When clear, upstream memory reads will be forwarded to fabric using fabric decode, unless specifically called out otherwise.
This bit can only be set if the platform does not support peer-to-peer memory reads.

25

0x1

RW

Upstream Posted Memory Write Peer Disable (UPMWPD)

When set, upstream posted memory writes will be forwarded to fabric using implicit decode, bypassing the peer decode phase. This results in shorter memory write latency to memory.
When clear, upstream posted memory writes will be forwarded to fabric using fabric decode, unless specifically called out otherwise.
This bit can only be set if the platform does not support peer-to-peer memory writes.
Upstream messages, such as MCTP are not subjected to this bit.

24

0x1

RW

Upstream Posted Split Disable (UPSD)

When '0', upstream posted memory requests will be split on boundaries defined by the UPRS bit in this register.
When '1' (default), upstream posted memory requests will not be split and will be presented to the backbone as received from the link.
This register has no effect on posted messages which are never split.
Note: This register is per-port. Software can independently enable or disable splitting for each ports.

23

0x0

RW

Upstream Non-Posted Split Disable (UNSD)

When '0', upstream non-posted requests will be split on boundaries defined by the UNRS bit in this register. When '1', upstream non-posted requests will not be split and will be presented to the backbone as received from the link. If configured not to split, the NPAP bit in this register must be set to '1' (never pre-allocate).
Note: This register is per-port. Software can independently enable or disable splitting for each ports.

22:17

0x0

RW

Non-Posted Pre-Allocation Size (NPAS)

This value is used when the NPAP in this register is set to 1. This field reserves the buffers in the Transmit Completion Queue based on the value programmed in this register.
000000: Completion Buffer size matching Credit advertised on IOSF Primary
000001: 256B (1 x 256B)
000010: 512B (2 x 256B)
....
Note: Software must ensure this register must not be programmed to a value more than the Transmit Completion Command Queue.

16

0x0

RW

Non-Posted Pre-Allocation Policy (NPAP)

Indicates whether pre-allocation of the shared resource should be performed. Valid encodings are:
Bits Description
0 Always Pre-allocate
1 Never Pre-Allocate
Note: This register is per-port. Software can independently enable or disable splitting for each ports.

15

0x0

RW

Dynamic Clock Gating Enable on ISM Active (DCGEISMA)

0: Shared resource dynamic clock gating is allowed when ISM is not in Idle state.
1: Shared resource dynamic clock gating is only allowed when ISM is in Idle state.
Note: Only Port 1 register is used.
This is a per controller register.

14

0h

RO

Reserved

13:12

0x0

RW

Upstream Non-Posted Request Delay (UNRD)

Sets the minimum delay between back-2-back non-posted read request puts on the IOSF backbone. The delay value is in 125 MHz backbone command clocks. Valid encodings are:
Bits Clock Delay
00 0 clocks
01 4 clocks
10 8 clocks
11 16 clocks

11

0x0

RW

Retry Buffers Minimum Size (RBMS)

When '0', retry buffer is sized according to port configuration: See Queue size table for queue sizes based on port configuration.
When '1', the retry command buffer is sized at minimum 1 cmd. This bit has no impact on data buffer sizing. This field can be modified only when the Link has been disabled LCTL.LD=1.

10

0h

RO

Reserved

9

0x0

RW

Minimum Receive Non-Posted Credits (MRNPC)

When set, allows only the minimum number of PCI Express receive credits for non-posted requests for this VC. For this to take effect, the Link Disable must be set.
Bits Description
0 Full credits based on configuration.
1 Minimum number of credits advertised (independent of configuration). 1 non-posted header, 1DW non-posted data
Note: PCI Express Completion receive credits are always infinite.

8

0x0

RW

Minimum Receive Posted Credits (MRPC)

When set, allows only the minimum number of PCI Express receive credits for posted requests for this VC. For this to take effect the Link Disable must be set.
Bits Description
0 Full credits advertised based on configuration
1 Minimum number of credits advertised (independent of configuration): 1 posted header, 8 or 16 posted data (128B or 256B depending on max payload size)

7

0h

RO

Reserved

6:4

0x1

RW

Upstream Non-Posted Request Size (UNRS)

Sets the size for splitting upstream memory read requests. Requests will be split on naturally aligned addresses.
Defined encodings for this field are:
000b: 128 byte boundaries.
001b: 256 byte boundaries.
010b: 512 byte boundaries.
011b - 110b: Reserved. 128 byte boundaries.
111b: 64 byte boundaries.
Note: This register is per-port. Software can program the request size to be different for different ports.
Only '000b', '001b' and '111b' are supported. '010b' is not a POR setting.
This field is only used if the Upstream Non-Posted Split Disable is '0'.

3

0h

RO

Reserved

2:0

0x1

RW

Upstream Posted Request Size (UPRS)

Sets the size for splitting upstream memory write requests. Requests will be split on naturally aligned addresses.
Defined encodings for this field are:
000b: 128 byte boundaries.
001b: 256 byte boundaries.
010b: 512 byte boundaries.
011b - 110b: Reserved. 128 byte boundaries.
111b: 64 byte boundaries.
This field must not be set more than the effective Maximum Payload Size (function of both DCAP.MPS and DCTL.MPS).
Note: This register is per-port. Software can program the request size to be different for different ports.
Only '000b', '001b' and '111b' are supported. '010b' is not a POR setting.
This field is only used if the Upstream Posted Split Disable is '0'. This register has no effect on posted messages which are never split.